Documentation/devicetree/bindings/arm/idle-states.txt

   1 ==========================================
   2 ARM idle states binding description
   3 ==========================================
   4
   5 ==========================================
   6 1 - Introduction
   7 ==========================================
   8
   9 ARM systems contain HW capable of managing power consumption dynamically,
  10 where cores can be put in different low-power states (ranging from simple
  11 wfi to power gating) according to OS PM policies. The CPU states representing
  12 the range of dynamic idle states that a processor can enter at run-time, can be
  13 specified through device tree bindings representing the parameters required
  14 to enter/exit specific idle states on a given processor.
  15
  16 According to the Server Base System Architecture document (SBSA, [3]), the
  17 power states an ARM CPU can be put into are identified by the following list:
  18
  19 - Running
  20 - Idle_standby
  21 - Idle_retention
  22 - Sleep
  23 - Off
  24
  25 The power states described in the SBSA document define the basic CPU states on
  26 top of which ARM platforms implement power management schemes that allow an OS
  27 PM implementation to put the processor in different idle states (which include
  28 states listed above; "off" state is not an idle state since it does not have
  29 wake-up capabilities, hence it is not considered in this document).
  30
  31 Idle state parameters (eg entry latency) are platform specific and need to be
  32 characterized with bindings that provide the required information to OS PM
  33 code so that it can build the required tables and use them at runtime.
  34
  35 The device tree binding definition for ARM idle states is the subject of this
  36 document.
  37
  38 ===========================================
  39 2 - idle-states definitions
  40 ===========================================
  41
  42 Idle states are characterized for a specific system through a set of
  43 timing and energy related properties, that underline the HW behaviour
  44 triggered upon idle states entry and exit.
  45
  46 The following diagram depicts the CPU execution phases and related timing
  47 properties required to enter and exit an idle state:
  48
  49 ..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
  50             |          |           |          |          |
  51
  52             |<------ entry ------->|
  53             |       latency        |
  54                                               |<- exit ->|
  55                                               |  latency |
  56             |<-------- min-residency -------->|
  57                        |<-------  wakeup-latency ------->|
  58
  59                 Diagram 1: CPU idle state execution phases
  60
  61 EXEC:   Normal CPU execution.
  62
  63 PREP:   Preparation phase before committing the hardware to idle mode
  64         like cache flushing. This is abortable on pending wake-up
  65         event conditions. The abort latency is assumed to be negligible
  66         (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
  67         goes back to EXEC. This phase is optional. If not abortable,
  68         this should be included in the ENTRY phase instead.
  69
  70 ENTRY:  The hardware is committed to idle mode. This period must run
  71         to completion up to IDLE before anything else can happen.
  72
  73 IDLE:   This is the actual energy-saving idle period. This may last
  74         between 0 and infinite time, until a wake-up event occurs.
  75
  76 EXIT:   Period during which the CPU is brought back to operational
  77         mode (EXEC).
  78
  79 entry-latency: Worst case latency required to enter the idle state. The
  80 exit-latency may be guaranteed only after entry-latency has passed.
  81
  82 min-residency: Minimum period, including preparation and entry, for a given
  83 idle state to be worthwhile energywise.
  84
  85 wakeup-latency: Maximum delay between the signaling of a wake-up event and the
  86 CPU being able to execute normal code again. If not specified, this is assumed
  87 to be entry-latency + exit-latency.
  88
  89 These timing parameters can be used by an OS in different circumstances.
  90
  91 An idle CPU requires the expected min-residency time to select the most
  92 appropriate idle state based on the expected expiry time of the next IRQ
  93 (ie wake-up) that causes the CPU to return to the EXEC phase.
  94
  95 An operating system scheduler may need to compute the shortest wake-up delay
  96 for CPUs in the system by detecting how long will it take to get a CPU out
  97 of an idle state, eg:
  98
  99 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
 100
 101 In other words, the scheduler can make its scheduling decision by selecting
 102 (eg waking-up) the CPU with the shortest wake-up latency.
 103 The wake-up latency must take into account the entry latency if that period
 104 has not expired. The abortable nature of the PREP period can be ignored
 105 if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
 106 the worst case since it depends on the CPU operating conditions, ie caches
 107 state).
 108
 109 An OS has to reliably probe the wakeup-latency since some devices can enforce
 110 latency constraints guarantees to work properly, so the OS has to detect the
 111 worst case wake-up latency it can incur if a CPU is allowed to enter an
 112 idle state, and possibly to prevent that to guarantee reliable device
 113 functioning.
 114
 115 The min-residency time parameter deserves further explanation since it is
 116 expressed in time units but must factor in energy consumption coefficients.
 117
 118 The energy consumption of a cpu when it enters a power state can be roughly
 119 characterised by the following graph:
 120
 121                |
 122                |
 123                |
 124            e   |
 125            n   |                                      /---
 126            e   |                               /------
 127            r   |                        /------
 128            g   |                  /-----
 129            y   |           /------
 130                |       ----
 131                |      /|
 132                |     / |
 133                |    /  |
 134                |   /   |
 135                |  /    |
 136                | /     |
 137                |/      |
 138           -----|-------+----------------------------------
 139               0|       1                              time(ms)
 140
 141                 Graph 1: Energy vs time example
 142
 143 The graph is split in two parts delimited by time 1ms on the X-axis.
 144 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
 145 and denotes the energy costs incurred whilst entering and leaving the idle
 146 state.
 147 The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
 148 shallower slope and essentially represents the energy consumption of the idle
 149 state.
 150
 151 min-residency is defined for a given idle state as the minimum expected
 152 residency time for a state (inclusive of preparation and entry) after
 153 which choosing that state become the most energy efficient option. A good
 154 way to visualise this, is by taking the same graph above and comparing some
 155 states energy consumptions plots.
 156
 157 For sake of simplicity, let's consider a system with two idle states IDLE1,
 158 and IDLE2:
 159
 160           |
 161           |
 162           |
 163           |                                                  /-- IDLE1
 164        e  |                                              /---
 165        n  |                                         /----
 166        e  |                                     /---
 167        r  |                                /-----/--------- IDLE2
 168        g  |                    /-------/---------
 169        y  |        ------------    /---|
 170           |       /           /----    |
 171           |      /        /---         |
 172           |     /    /----             |
 173           |    / /---                  |
 174           |   ---                      |
 175           |  /                         |
 176           | /                          |
 177           |/                           |                  time
 178        ---/----------------------------+------------------------
 179           |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
 180                                        |
 181                                 IDLE2-min-residency
 182
 183                 Graph 2: idle states min-residency example
 184
 185 In graph 2 above, that takes into account idle states entry/exit energy
 186 costs, it is clear that if the idle state residency time (ie time till next
 187 wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
 188 choice energywise.
 189
 190 This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
 191 than IDLE2.
 192
 193 However, the lower power consumption (ie shallower energy curve slope) of idle
 194 state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
 195 efficient.
 196
 197 The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
 198 shallower states in a system with multiple idle states) is defined
 199 IDLE2-min-residency and corresponds to the time when energy consumption of
 200 IDLE1 and IDLE2 states breaks even.
 201
 202 The definitions provided in this section underpin the idle states
 203 properties specification that is the subject of the following sections.
 204
 205 ===========================================
 206 3 - idle-states node
 207 ===========================================
 208
 209 ARM processor idle states are defined within the idle-states node, which is
 210 a direct child of the cpus node [1] and provides a container where the
 211 processor idle states, defined as device tree nodes, are listed.
 212
 213 - idle-states node
 214
 215         Usage: Optional - On ARM systems, it is a container of processor idle
 216                           states nodes. If the system does not provide CPU
 217                           power management capabilities or the processor just
 218                           supports idle_standby an idle-states node is not
 219                           required.
 220
 221         Description: idle-states node is a container node, where its
 222                      subnodes describe the CPU idle states.
 223
 224         Node name must be "idle-states".
 225
 226         The idle-states node's parent node must be the cpus node.
 227
 228         The idle-states node's child nodes can be:
 229
 230         - one or more state nodes
 231
 232         Any other configuration is considered invalid.
 233
 234         An idle-states node defines the following properties:
 235
 236         - entry-method
 237                 Value type: <stringlist>
 238                 Usage and definition depend on ARM architecture version.
 239                         # On ARM v8 64-bit this property is required and must
 240                           be one of:
 241                            - "psci" (see bindings in [2])
 242                         # On ARM 32-bit systems this property is optional
 243
 244 The nodes describing the idle states (state) can only be defined within the
 245 idle-states node, any other configuration is considered invalid and therefore
 246 must be ignored.
 247
 248 ===========================================
 249 4 - state node
 250 ===========================================
 251
 252 A state node represents an idle state description and must be defined as
 253 follows:
 254
 255 - state node
 256
 257         Description: must be child of the idle-states node
 258
 259         The state node name shall follow standard device tree naming
 260         rules ([5], 2.2.1 "Node names"), in particular state nodes which
 261         are siblings within a single common parent must be given a unique name.
 262
 263         The idle state entered by executing the wfi instruction (idle_standby
 264         SBSA,[3][4]) is considered standard on all ARM platforms and therefore
 265         must not be listed.
 266
 267         With the definitions provided above, the following list represents
 268         the valid properties for a state node:
 269
 270         - compatible
 271                 Usage: Required
 272                 Value type: <stringlist>
 273                 Definition: Must be "arm,idle-state".
 274
 275         - local-timer-stop
 276                 Usage: See definition
 277                 Value type: <none>
 278                 Definition: if present the CPU local timer control logic is
 279                             lost on state entry, otherwise it is retained.
 280
 281         - entry-latency-us
 282                 Usage: Required
 283                 Value type: <prop-encoded-array>
 284                 Definition: u32 value representing worst case latency in
 285                             microseconds required to enter the idle state.
 286                             The exit-latency-us duration may be guaranteed
 287                             only after entry-latency-us has passed.
 288
 289         - exit-latency-us
 290                 Usage: Required
 291                 Value type: <prop-encoded-array>
 292                 Definition: u32 value representing worst case latency
 293                             in microseconds required to exit the idle state.
 294
 295         - min-residency-us
 296                 Usage: Required
 297                 Value type: <prop-encoded-array>
 298                 Definition: u32 value representing minimum residency duration
 299                             in microseconds, inclusive of preparation and
 300                             entry, for this idle state to be considered
 301                             worthwhile energy wise (refer to section 2 of
 302                             this document for a complete description).
 303
 304         - wakeup-latency-us:
 305                 Usage: Optional
 306                 Value type: <prop-encoded-array>
 307                 Definition: u32 value representing maximum delay between the
 308                             signaling of a wake-up event and the CPU being
 309                             able to execute normal code again. If omitted,
 310                             this is assumed to be equal to:
 311
 312                                 entry-latency-us + exit-latency-us
 313
 314                             It is important to supply this value on systems
 315                             where the duration of PREP phase (see diagram 1,
 316                             section 2) is non-neglibigle.
 317                             In such systems entry-latency-us + exit-latency-us
 318                             will exceed wakeup-latency-us by this duration.
 319
 320         In addition to the properties listed above, a state node may require
 321         additional properties specifics to the entry-method defined in the
 322         idle-states node, please refer to the entry-method bindings
 323         documentation for properties definitions.
 324
 325 ===========================================
 326 4 - Examples
 327 ===========================================
 328
 329 Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
 330
 331 cpus {
 332         #size-cells = <0>;
 333         #address-cells = <2>;
 334
 335         CPU0: cpu@0 {
 336                 device_type = "cpu";
 337                 compatible = "arm,cortex-a57";
 338                 reg = <0x0 0x0>;
 339                 enable-method = "psci";
 340                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 341                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 342         };
 343
 344         CPU1: cpu@1 {
 345                 device_type = "cpu";
 346                 compatible = "arm,cortex-a57";
 347                 reg = <0x0 0x1>;
 348                 enable-method = "psci";
 349                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 350                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 351         };
 352
 353         CPU2: cpu@100 {
 354                 device_type = "cpu";
 355                 compatible = "arm,cortex-a57";
 356                 reg = <0x0 0x100>;
 357                 enable-method = "psci";
 358                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 359                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 360         };
 361
 362         CPU3: cpu@101 {
 363                 device_type = "cpu";
 364                 compatible = "arm,cortex-a57";
 365                 reg = <0x0 0x101>;
 366                 enable-method = "psci";
 367                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 368                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 369         };
 370
 371         CPU4: cpu@10000 {
 372                 device_type = "cpu";
 373                 compatible = "arm,cortex-a57";
 374                 reg = <0x0 0x10000>;
 375                 enable-method = "psci";
 376                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 377                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 378         };
 379
 380         CPU5: cpu@10001 {
 381                 device_type = "cpu";
 382                 compatible = "arm,cortex-a57";
 383                 reg = <0x0 0x10001>;
 384                 enable-method = "psci";
 385                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 386                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 387         };
 388
 389         CPU6: cpu@10100 {
 390                 device_type = "cpu";
 391                 compatible = "arm,cortex-a57";
 392                 reg = <0x0 0x10100>;
 393                 enable-method = "psci";
 394                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 395                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 396         };
 397
 398         CPU7: cpu@10101 {
 399                 device_type = "cpu";
 400                 compatible = "arm,cortex-a57";
 401                 reg = <0x0 0x10101>;
 402                 enable-method = "psci";
 403                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 404                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 405         };
 406
 407         CPU8: cpu@100000000 {
 408                 device_type = "cpu";
 409                 compatible = "arm,cortex-a53";
 410                 reg = <0x1 0x0>;
 411                 enable-method = "psci";
 412                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 413                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 414         };
 415
 416         CPU9: cpu@100000001 {
 417                 device_type = "cpu";
 418                 compatible = "arm,cortex-a53";
 419                 reg = <0x1 0x1>;
 420                 enable-method = "psci";
 421                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 422                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 423         };
 424
 425         CPU10: cpu@100000100 {
 426                 device_type = "cpu";
 427                 compatible = "arm,cortex-a53";
 428                 reg = <0x1 0x100>;
 429                 enable-method = "psci";
 430                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 431                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 432         };
 433
 434         CPU11: cpu@100000101 {
 435                 device_type = "cpu";
 436                 compatible = "arm,cortex-a53";
 437                 reg = <0x1 0x101>;
 438                 enable-method = "psci";
 439                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 440                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 441         };
 442
 443         CPU12: cpu@100010000 {
 444                 device_type = "cpu";
 445                 compatible = "arm,cortex-a53";
 446                 reg = <0x1 0x10000>;
 447                 enable-method = "psci";
 448                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 449                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 450         };
 451
 452         CPU13: cpu@100010001 {
 453                 device_type = "cpu";
 454                 compatible = "arm,cortex-a53";
 455                 reg = <0x1 0x10001>;
 456                 enable-method = "psci";
 457                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 458                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 459         };
 460
 461         CPU14: cpu@100010100 {
 462                 device_type = "cpu";
 463                 compatible = "arm,cortex-a53";
 464                 reg = <0x1 0x10100>;
 465                 enable-method = "psci";
 466                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 467                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 468         };
 469
 470         CPU15: cpu@100010101 {
 471                 device_type = "cpu";
 472                 compatible = "arm,cortex-a53";
 473                 reg = <0x1 0x10101>;
 474                 enable-method = "psci";
 475                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 476                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 477         };
 478
 479         idle-states {
 480                 entry-method = "arm,psci";
 481
 482                 CPU_RETENTION_0_0: cpu-retention-0-0 {
 483                         compatible = "arm,idle-state";
 484                         arm,psci-suspend-param = <0x0010000>;
 485                         entry-latency-us = <20>;
 486                         exit-latency-us = <40>;
 487                         min-residency-us = <80>;
 488                 };
 489
 490                 CLUSTER_RETENTION_0: cluster-retention-0 {
 491                         compatible = "arm,idle-state";
 492                         local-timer-stop;
 493                         arm,psci-suspend-param = <0x1010000>;
 494                         entry-latency-us = <50>;
 495                         exit-latency-us = <100>;
 496                         min-residency-us = <250>;
 497                         wakeup-latency-us = <130>;
 498                 };
 499
 500                 CPU_SLEEP_0_0: cpu-sleep-0-0 {
 501                         compatible = "arm,idle-state";
 502                         local-timer-stop;
 503                         arm,psci-suspend-param = <0x0010000>;
 504                         entry-latency-us = <250>;
 505                         exit-latency-us = <500>;
 506                         min-residency-us = <950>;
 507                 };
 508
 509                 CLUSTER_SLEEP_0: cluster-sleep-0 {
 510                         compatible = "arm,idle-state";
 511                         local-timer-stop;
 512                         arm,psci-suspend-param = <0x1010000>;
 513                         entry-latency-us = <600>;
 514                         exit-latency-us = <1100>;
 515                         min-residency-us = <2700>;
 516                         wakeup-latency-us = <1500>;
 517                 };
 518
 519                 CPU_RETENTION_1_0: cpu-retention-1-0 {
 520                         compatible = "arm,idle-state";
 521                         arm,psci-suspend-param = <0x0010000>;
 522                         entry-latency-us = <20>;
 523                         exit-latency-us = <40>;
 524                         min-residency-us = <90>;
 525                 };
 526
 527                 CLUSTER_RETENTION_1: cluster-retention-1 {
 528                         compatible = "arm,idle-state";
 529                         local-timer-stop;
 530                         arm,psci-suspend-param = <0x1010000>;
 531                         entry-latency-us = <50>;
 532                         exit-latency-us = <100>;
 533                         min-residency-us = <270>;
 534                         wakeup-latency-us = <100>;
 535                 };
 536
 537                 CPU_SLEEP_1_0: cpu-sleep-1-0 {
 538                         compatible = "arm,idle-state";
 539                         local-timer-stop;
 540                         arm,psci-suspend-param = <0x0010000>;
 541                         entry-latency-us = <70>;
 542                         exit-latency-us = <100>;
 543                         min-residency-us = <300>;
 544                         wakeup-latency-us = <150>;
 545                 };
 546
 547                 CLUSTER_SLEEP_1: cluster-sleep-1 {
 548                         compatible = "arm,idle-state";
 549                         local-timer-stop;
 550                         arm,psci-suspend-param = <0x1010000>;
 551                         entry-latency-us = <500>;
 552                         exit-latency-us = <1200>;
 553                         min-residency-us = <3500>;
 554                         wakeup-latency-us = <1300>;
 555                 };
 556         };
 557
 558 };
 559
 560 Example 2 (ARM 32-bit, 8-cpu system, two clusters):
 561
 562 cpus {
 563         #size-cells = <0>;
 564         #address-cells = <1>;
 565
 566         CPU0: cpu@0 {
 567                 device_type = "cpu";
 568                 compatible = "arm,cortex-a15";
 569                 reg = <0x0>;
 570                 cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
 571         };
 572
 573         CPU1: cpu@1 {
 574                 device_type = "cpu";
 575                 compatible = "arm,cortex-a15";
 576                 reg = <0x1>;
 577                 cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
 578         };
 579
 580         CPU2: cpu@2 {
 581                 device_type = "cpu";
 582                 compatible = "arm,cortex-a15";
 583                 reg = <0x2>;
 584                 cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
 585         };
 586
 587         CPU3: cpu@3 {
 588                 device_type = "cpu";
 589                 compatible = "arm,cortex-a15";
 590                 reg = <0x3>;
 591                 cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
 592         };
 593
 594         CPU4: cpu@100 {
 595                 device_type = "cpu";
 596                 compatible = "arm,cortex-a7";
 597                 reg = <0x100>;
 598                 cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
 599         };
 600
 601         CPU5: cpu@101 {
 602                 device_type = "cpu";
 603                 compatible = "arm,cortex-a7";
 604                 reg = <0x101>;
 605                 cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
 606         };
 607
 608         CPU6: cpu@102 {
 609                 device_type = "cpu";
 610                 compatible = "arm,cortex-a7";
 611                 reg = <0x102>;
 612                 cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
 613         };
 614
 615         CPU7: cpu@103 {
 616                 device_type = "cpu";
 617                 compatible = "arm,cortex-a7";
 618                 reg = <0x103>;
 619                 cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
 620         };
 621
 622         idle-states {
 623                 CPU_SLEEP_0_0: cpu-sleep-0-0 {
 624                         compatible = "arm,idle-state";
 625                         local-timer-stop;
 626                         entry-latency-us = <200>;
 627                         exit-latency-us = <100>;
 628                         min-residency-us = <400>;
 629                         wakeup-latency-us = <250>;
 630                 };
 631
 632                 CLUSTER_SLEEP_0: cluster-sleep-0 {
 633                         compatible = "arm,idle-state";
 634                         local-timer-stop;
 635                         entry-latency-us = <500>;
 636                         exit-latency-us = <1500>;
 637                         min-residency-us = <2500>;
 638                         wakeup-latency-us = <1700>;
 639                 };
 640
 641                 CPU_SLEEP_1_0: cpu-sleep-1-0 {
 642                         compatible = "arm,idle-state";
 643                         local-timer-stop;
 644                         entry-latency-us = <300>;
 645                         exit-latency-us = <500>;
 646                         min-residency-us = <900>;
 647                         wakeup-latency-us = <600>;
 648                 };
 649
 650                 CLUSTER_SLEEP_1: cluster-sleep-1 {
 651                         compatible = "arm,idle-state";
 652                         local-timer-stop;
 653                         entry-latency-us = <800>;
 654                         exit-latency-us = <2000>;
 655                         min-residency-us = <6500>;
 656                         wakeup-latency-us = <2300>;
 657                 };
 658         };
 659
 660 };
 661
 662 ===========================================
 663 5 - References
 664 ===========================================
 665
 666 [1] ARM Linux Kernel documentation - CPUs bindings
 667     Documentation/devicetree/bindings/arm/cpus.txt
 668
 669 [2] ARM Linux Kernel documentation - PSCI bindings
 670     Documentation/devicetree/bindings/arm/psci.txt
 671
 672 [3] ARM Server Base System Architecture (SBSA)
 673     http://infocenter.arm.com/help/index.jsp
 674
 675 [4] ARM Architecture Reference Manuals
 676     http://infocenter.arm.com/help/index.jsp
 677
 678 [5] ePAPR standard
 679     https://www.power.org/documentation/epapr-version-1-1/