1 Hisilicon Platforms Device Tree Bindings
2 ----------------------------------------------------
4 Required root node properties:
5 - compatible = "hisilicon,hi3660";
8 Required root node properties:
9 - compatible = "hisilicon,hi3620-hi4511";
12 Required root node properties:
13 - compatible = "hisilicon,hi6220";
16 Required root node properties:
17 - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
20 Required root node properties:
21 - compatible = "hisilicon,hip01-ca9x2";
24 Required root node properties:
25 - compatible = "hisilicon,hip04-d01";
28 Required root node properties:
29 - compatible = "hisilicon,hip05-d02";
32 Required root node properties:
33 - compatible = "hisilicon,hip06-d03";
36 Required root node properties:
37 - compatible = "hisilicon,hip07-d05";
39 Hisilicon system controller
42 - compatible : "hisilicon,sysctrl"
43 - reg : Register address and size
46 - smp-offset : offset in sysctrl for notifying slave cpu booting
50 If reg value is not zero, cpun exit wfi and go
51 - resume-offset : offset in sysctrl for notifying cpu0 when resume
52 - reboot-offset : offset in sysctrl for system reboot
57 sysctrl: system-controller@fc802000 {
58 compatible = "hisilicon,sysctrl";
59 reg = <0xfc802000 0x1000>;
61 resume-offset = <0x308>;
62 reboot-offset = <0x4>;
65 -----------------------------------------------------------------------
66 Hisilicon Hi6220 system controller
69 - compatible : "hisilicon,hi6220-sysctrl"
70 - reg : Register address and size
71 - #clock-cells: should be set to 1, many clock registers are defined
72 under this controller and this property must be present.
74 Hisilicon designs this controller as one of the system controllers,
75 its main functions are the same as Hisilicon system controller, but
76 the register offset of some core modules are different.
80 sys_ctrl: sys_ctrl@f7030000 {
81 compatible = "hisilicon,hi6220-sysctrl", "syscon";
82 reg = <0x0 0xf7030000 0x0 0x2000>;
87 Hisilicon Hi6220 Power Always ON domain controller
90 - compatible : "hisilicon,hi6220-aoctrl"
91 - reg : Register address and size
92 - #clock-cells: should be set to 1, many clock registers are defined
93 under this controller and this property must be present.
95 Hisilicon designs this system controller to control the power always
96 on domain for mobile platform.
100 ao_ctrl: ao_ctrl@f7800000 {
101 compatible = "hisilicon,hi6220-aoctrl", "syscon";
102 reg = <0x0 0xf7800000 0x0 0x2000>;
107 Hisilicon Hi6220 Media domain controller
110 - compatible : "hisilicon,hi6220-mediactrl"
111 - reg : Register address and size
112 - #clock-cells: should be set to 1, many clock registers are defined
113 under this controller and this property must be present.
115 Hisilicon designs this system controller to control the multimedia
116 domain(e.g. codec, G3D ...) for mobile platform.
120 media_ctrl: media_ctrl@f4410000 {
121 compatible = "hisilicon,hi6220-mediactrl", "syscon";
122 reg = <0x0 0xf4410000 0x0 0x1000>;
127 Hisilicon Hi6220 Power Management domain controller
130 - compatible : "hisilicon,hi6220-pmctrl"
131 - reg : Register address and size
132 - #clock-cells: should be set to 1, some clock registers are define
133 under this controller and this property must be present.
135 Hisilicon designs this system controller to control the power management
136 domain for mobile platform.
140 pm_ctrl: pm_ctrl@f7032000 {
141 compatible = "hisilicon,hi6220-pmctrl", "syscon";
142 reg = <0x0 0xf7032000 0x0 0x1000>;
147 Hisilicon Hi6220 SRAM controller
150 - compatible : "hisilicon,hi6220-sramctrl", "syscon"
151 - reg : Register address and size
153 Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
154 SRAM banks for power management, modem, security, etc. Further, use "syscon"
155 managing the common sram which can be shared by multiple modules.
159 sram: sram@fff80000 {
160 compatible = "hisilicon,hi6220-sramctrl", "syscon";
161 reg = <0x0 0xfff80000 0x0 0x12000>;
164 -----------------------------------------------------------------------
165 Hisilicon HiP01 system controller
168 - compatible : "hisilicon,hip01-sysctrl"
169 - reg : Register address and size
171 The HiP01 system controller is mostly compatible with hisilicon
172 system controller,but it has some specific control registers for
173 HIP01 SoC family, such as slave core boot, and also some same
174 registers located at different offset.
178 /* for hip01-ca9x2 */
179 sysctrl: system-controller@10000000 {
180 compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
181 reg = <0x10000000 0x1000>;
182 reboot-offset = <0x4>;
185 -----------------------------------------------------------------------
186 Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
189 - compatible : "hisilicon,pcie-sas-subctrl", "syscon";
190 - reg : Register address and size
192 The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
193 HiP05 or HiP06 Soc to implement some basic configurations.
196 /* for HiP05 PCIe-SAS sub system */
197 pcie_sas: system_controller@b0000000 {
198 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
199 reg = <0xb0000000 0x10000>;
202 Hisilicon HiP05/HiP06 PERI sub system controller
205 - compatible : "hisilicon,peri-subctrl", "syscon";
206 - reg : Register address and size
208 The PERI sub system controller is shared by peripheral controllers in
209 HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
210 controllers include mdio, ddr, iic, uart, timer and so on.
213 /* for HiP05 sub peri system */
214 peri_c_subctrl: syscon@80000000 {
215 compatible = "hisilicon,peri-subctrl", "syscon";
216 reg = <0x0 0x80000000 0x0 0x10000>;
219 Hisilicon HiP05/HiP06 DSA sub system controller
222 - compatible : "hisilicon,dsa-subctrl", "syscon";
223 - reg : Register address and size
225 The DSA sub system controller is shared by peripheral controllers in
226 HiP05 or HiP06 Soc to implement some basic configurations.
229 /* for HiP05 dsa sub system */
230 pcie_sas: system_controller@a0000000 {
231 compatible = "hisilicon,dsa-subctrl", "syscon";
232 reg = <0xa0000000 0x10000>;
235 -----------------------------------------------------------------------
236 Hisilicon CPU controller
239 - compatible : "hisilicon,cpuctrl"
240 - reg : Register address and size
242 The clock registers and power registers of secondary cores are defined
243 in CPU controller, especially in HIX5HD2 SoC.
245 -----------------------------------------------------------------------
246 PCTRL: Peripheral misc control register
249 - compatible: "hisilicon,pctrl"
250 - reg: Address and size of pctrl.
255 pctrl: pctrl@fca09000 {
256 compatible = "hisilicon,pctrl";
257 reg = <0xfca09000 0x1000>;
260 -----------------------------------------------------------------------
264 - compatible: "hisilicon,hip04-fabric";
265 - reg: Address and size of Fabric
267 -----------------------------------------------------------------------
268 Bootwrapper boot method (software protocol on SMP):
271 - compatible: "hisilicon,hip04-bootwrapper";
272 - boot-method: Address and size of boot method.
273 [0]: bootwrapper physical address
274 [1]: bootwrapper size
275 [2]: relocation physical address