1 NXP i.MX System Controller Firmware (SCFW)
2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
6 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
7 (QM, QP), and i.MX8QX (QXP, DX).
9 The AP communicates with the SC using a multi-ported MU module found
10 in the LSIO subsystem. The current definition of this MU module provides
11 5 remote AP connections to the SC to support up to 5 execution environments
12 (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
13 with the LSIO DSC IP bus. The SC firmware will communicate with this MU
16 System Controller Device Node:
17 ============================================================
19 The scu node with the following properties shall be under the /firmware/ node.
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
25 "rx0", "rx1", "rx2", "rx3".
26 - mboxes: List of phandle of 4 MU channels for tx and 4 MU channels
27 for rx. All 8 MU channels must be in the same MU instance.
28 Cross instances are not allowed. The MU instance can only
29 be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
30 to make sure use the one which is not conflict with other
31 execution environments. e.g. ATF.
33 Channel 0 must be "tx0" or "rx0".
34 Channel 1 must be "tx1" or "rx1".
35 Channel 2 must be "tx2" or "rx2".
36 Channel 3 must be "tx3" or "rx3".
38 mboxes = <&lsio_mu1 0 0
46 See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
47 for detailed mailbox binding.
49 i.MX SCU Client Device Node:
50 ============================================================
52 Client nodes are maintained as children of the relevant IMX-SCU device node.
54 Power domain bindings based on SCU Message Protocol
55 ------------------------------------------------------------
57 This binding for the SCU power domain providers uses the generic power
61 - compatible: Should be one of:
64 followed by "fsl,scu-pd"
66 - #power-domain-cells: Must be 1. Contains the Resource ID used by
68 See detailed Resource ID list from:
69 include/dt-bindings/firmware/imx/rsrc.h
71 Clock bindings based on SCU Message Protocol
72 ------------------------------------------------------------
74 This binding uses the common clock binding[1].
77 - compatible: Should be one of:
80 followed by "fsl,scu-clk"
81 - #clock-cells: Should be 1. Contains the Clock ID value.
82 - clocks: List of clock specifiers, must contain an entry for
83 each required entry in clock-names
84 - clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
86 The clock consumer should specify the desired clock by having the clock
87 ID in its "clocks" phandle cell.
89 See the full list of clock IDs from:
90 include/dt-bindings/clock/imx8qxp-clock.h
92 Pinctrl bindings based on SCU Message Protocol
93 ------------------------------------------------------------
95 This binding uses the i.MX common pinctrl binding[3].
98 - compatible: Should be one of:
100 "fsl,imx8qxp-iomuxc".
102 Required properties for Pinctrl sub nodes:
103 - fsl,pins: Each entry consists of 3 integers which represents
104 the mux and config setting for one pin. The first 2
105 integers <pin_id mux_mode> are specified using a
106 PIN_FUNC_ID macro, which can be found in
107 <dt-bindings/pinctrl/pads-imx8qm.h>,
108 <dt-bindings/pinctrl/pads-imx8qxp.h>.
109 The last integer CONFIG is the pad setting value like
112 Please refer to i.MX8QXP Reference Manual for detailed
115 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
116 [2] Documentation/devicetree/bindings/power/power_domain.txt
117 [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
119 RTC bindings based on SCU Message Protocol
120 ------------------------------------------------------------
123 - compatible: should be "fsl,imx8qxp-sc-rtc";
127 lsio_mu1: mailbox@5d1c0000 {
134 compatible = "fsl,imx-scu";
135 mbox-names = "tx0", "tx1", "tx2", "tx3",
136 "rx0", "rx1", "rx2", "rx3";
137 mboxes = <&lsio_mu1 0 0
147 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
152 compatible = "fsl,imx8qxp-iomuxc";
154 pinctrl_lpuart0: lpuart0grp {
156 SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
157 SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
164 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
165 #power-domain-cells = <1>;
169 compatible = "fsl,imx8qxp-sc-rtc";
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_lpuart0>;
178 clocks = <&clk IMX8QXP_UART0_CLK>,
179 <&clk IMX8QXP_UART0_IPG_CLK>;
180 clock-names = "per", "ipg";
181 power-domains = <&pd IMX_SC_R_UART_0>;