Documentation/devicetree/bindings/arm/cpus.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: ARM CPUs bindings
   8
   9 maintainers:
  10   - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  11
  12 description: |+
  13   The device tree allows to describe the layout of CPUs in a system through
  14   the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
  15   defining properties for every cpu.
  16
  17   Bindings for CPU nodes follow the Devicetree Specification, available from:
  18
  19   https://www.devicetree.org/specifications/
  20
  21   with updates for 32-bit and 64-bit ARM systems provided in this document.
  22
  23   ================================
  24   Convention used in this document
  25   ================================
  26
  27   This document follows the conventions described in the Devicetree
  28   Specification, with the addition:
  29
  30   - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  31     the reg property contained in bits 7 down to 0
  32
  33   =====================================
  34   cpus and cpu node bindings definition
  35   =====================================
  36
  37   The ARM architecture, in accordance with the Devicetree Specification,
  38   requires the cpus and cpu nodes to be present and contain the properties
  39   described below.
  40
  41 properties:
  42   $nodename:
  43     const: cpus
  44     description: Container of cpu nodes
  45
  46   '#address-cells':
  47     enum: [1, 2]
  48     description: |
  49       Definition depends on ARM architecture version and configuration:
  50
  51       On uniprocessor ARM architectures previous to v7
  52         value must be 1, to enable a simple enumeration
  53         scheme for processors that do not have a HW CPU
  54         identification register.
  55       On 32-bit ARM 11 MPcore, ARM v7 or later systems
  56         value must be 1, that corresponds to CPUID/MPIDR
  57         registers sizes.
  58       On ARM v8 64-bit systems value should be set to 2,
  59         that corresponds to the MPIDR_EL1 register size.
  60         If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
  61         in the system, #address-cells can be set to 1, since
  62         MPIDR_EL1[63:32] bits are not used for CPUs
  63         identification.
  64
  65   '#size-cells':
  66     const: 0
  67
  68 patternProperties:
  69   '^cpu@[0-9a-f]+$':
  70     properties:
  71       device_type:
  72         const: cpu
  73
  74       reg:
  75         maxItems: 1
  76         description: |
  77           Usage and definition depend on ARM architecture version and
  78           configuration:
  79
  80           On uniprocessor ARM architectures previous to v7
  81           this property is required and must be set to 0.
  82
  83           On ARM 11 MPcore based systems this property is
  84             required and matches the CPUID[11:0] register bits.
  85
  86             Bits [11:0] in the reg cell must be set to
  87             bits [11:0] in CPU ID register.
  88
  89             All other bits in the reg cell must be set to 0.
  90
  91           On 32-bit ARM v7 or later systems this property is
  92             required and matches the CPU MPIDR[23:0] register
  93             bits.
  94
  95             Bits [23:0] in the reg cell must be set to
  96             bits [23:0] in MPIDR.
  97
  98             All other bits in the reg cell must be set to 0.
  99
 100           On ARM v8 64-bit systems this property is required
 101             and matches the MPIDR_EL1 register affinity bits.
 102
 103             * If cpus node's #address-cells property is set to 2
 104
 105               The first reg cell bits [7:0] must be set to
 106               bits [39:32] of MPIDR_EL1.
 107
 108               The second reg cell bits [23:0] must be set to
 109               bits [23:0] of MPIDR_EL1.
 110
 111             * If cpus node's #address-cells property is set to 1
 112
 113               The reg cell bits [23:0] must be set to bits [23:0]
 114               of MPIDR_EL1.
 115
 116           All other bits in the reg cells must be set to 0.
 117
 118       compatible:
 119         items:
 120           - enum:
 121               - arm,arm710t
 122               - arm,arm720t
 123               - arm,arm740t
 124               - arm,arm7ej-s
 125               - arm,arm7tdmi
 126               - arm,arm7tdmi-s
 127               - arm,arm9es
 128               - arm,arm9ej-s
 129               - arm,arm920t
 130               - arm,arm922t
 131               - arm,arm925
 132               - arm,arm926e-s
 133               - arm,arm926ej-s
 134               - arm,arm940t
 135               - arm,arm946e-s
 136               - arm,arm966e-s
 137               - arm,arm968e-s
 138               - arm,arm9tdmi
 139               - arm,arm1020e
 140               - arm,arm1020t
 141               - arm,arm1022e
 142               - arm,arm1026ej-s
 143               - arm,arm1136j-s
 144               - arm,arm1136jf-s
 145               - arm,arm1156t2-s
 146               - arm,arm1156t2f-s
 147               - arm,arm1176jzf
 148               - arm,arm1176jz-s
 149               - arm,arm1176jzf-s
 150               - arm,arm11mpcore
 151               - arm,armv8 # Only for s/w models
 152               - arm,cortex-a5
 153               - arm,cortex-a7
 154               - arm,cortex-a8
 155               - arm,cortex-a9
 156               - arm,cortex-a12
 157               - arm,cortex-a15
 158               - arm,cortex-a17
 159               - arm,cortex-a53
 160               - arm,cortex-a57
 161               - arm,cortex-a72
 162               - arm,cortex-a73
 163               - arm,cortex-m0
 164               - arm,cortex-m0+
 165               - arm,cortex-m1
 166               - arm,cortex-m3
 167               - arm,cortex-m4
 168               - arm,cortex-r4
 169               - arm,cortex-r5
 170               - arm,cortex-r7
 171               - brcm,brahma-b15
 172               - brcm,brahma-b53
 173               - brcm,vulcan
 174               - cavium,thunder
 175               - cavium,thunder2
 176               - faraday,fa526
 177               - intel,sa110
 178               - intel,sa1100
 179               - marvell,feroceon
 180               - marvell,mohawk
 181               - marvell,pj4a
 182               - marvell,pj4b
 183               - marvell,sheeva-v5
 184               - marvell,sheeva-v7
 185               - nvidia,tegra132-denver
 186               - nvidia,tegra186-denver
 187               - nvidia,tegra194-carmel
 188               - qcom,krait
 189               - qcom,kryo
 190               - qcom,kryo385
 191               - qcom,scorpion
 192
 193       enable-method:
 194         allOf:
 195           - $ref: '/schemas/types.yaml#/definitions/string'
 196           - oneOf:
 197             # On ARM v8 64-bit this property is required
 198             - enum:
 199                 - psci
 200                 - spin-table
 201             # On ARM 32-bit systems this property is optional
 202             - enum:
 203                 - actions,s500-smp
 204                 - allwinner,sun6i-a31
 205                 - allwinner,sun8i-a23
 206                 - allwinner,sun9i-a80-smp
 207                 - allwinner,sun8i-a83t-smp
 208                 - amlogic,meson8-smp
 209                 - amlogic,meson8b-smp
 210                 - arm,realview-smp
 211                 - brcm,bcm11351-cpu-method
 212                 - brcm,bcm23550
 213                 - brcm,bcm2836-smp
 214                 - brcm,bcm63138
 215                 - brcm,bcm-nsp-smp
 216                 - brcm,brahma-b15
 217                 - marvell,armada-375-smp
 218                 - marvell,armada-380-smp
 219                 - marvell,armada-390-smp
 220                 - marvell,armada-xp-smp
 221                 - marvell,98dx3236-smp
 222                 - mediatek,mt6589-smp
 223                 - mediatek,mt81xx-tz-smp
 224                 - qcom,gcc-msm8660
 225                 - qcom,kpss-acc-v1
 226                 - qcom,kpss-acc-v2
 227                 - renesas,apmu
 228                 - renesas,r9a06g032-smp
 229                 - rockchip,rk3036-smp
 230                 - rockchip,rk3066-smp
 231                 - ste,dbx500-smp
 232
 233       cpu-release-addr:
 234         $ref: '/schemas/types.yaml#/definitions/uint64'
 235
 236         description:
 237           Required for systems that have an "enable-method"
 238             property value of "spin-table".
 239           On ARM v8 64-bit systems must be a two cell
 240             property identifying a 64-bit zero-initialised
 241             memory location.
 242
 243       cpu-idle-states:
 244         $ref: '/schemas/types.yaml#/definitions/phandle-array'
 245         description: |
 246           List of phandles to idle state nodes supported
 247           by this cpu (see ./idle-states.txt).
 248
 249       capacity-dmips-mhz:
 250         $ref: '/schemas/types.yaml#/definitions/uint32'
 251         description:
 252           u32 value representing CPU capacity (see ./cpu-capacity.txt) in
 253           DMIPS/MHz, relative to highest capacity-dmips-mhz
 254           in the system.
 255
 256       dynamic-power-coefficient:
 257         $ref: '/schemas/types.yaml#/definitions/uint32'
 258         description:
 259           A u32 value that represents the running time dynamic
 260           power coefficient in units of uW/MHz/V^2. The
 261           coefficient can either be calculated from power
 262           measurements or derived by analysis.
 263
 264           The dynamic power consumption of the CPU  is
 265           proportional to the square of the Voltage (V) and
 266           the clock frequency (f). The coefficient is used to
 267           calculate the dynamic power as below -
 268
 269           Pdyn = dynamic-power-coefficient * V^2 * f
 270
 271           where voltage is in V, frequency is in MHz.
 272
 273       qcom,saw:
 274         $ref: '/schemas/types.yaml#/definitions/phandle'
 275         description: |
 276           Specifies the SAW* node associated with this CPU.
 277
 278           Required for systems that have an "enable-method" property
 279           value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
 280
 281           * arm/msm/qcom,saw2.txt
 282
 283       qcom,acc:
 284         $ref: '/schemas/types.yaml#/definitions/phandle'
 285         description: |
 286           Specifies the ACC* node associated with this CPU.
 287
 288           Required for systems that have an "enable-method" property
 289           value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
 290
 291           * arm/msm/qcom,kpss-acc.txt
 292
 293       rockchip,pmu:
 294         $ref: '/schemas/types.yaml#/definitions/phandle'
 295         description: |
 296           Specifies the syscon node controlling the cpu core power domains.
 297
 298           Optional for systems that have an "enable-method"
 299           property value of "rockchip,rk3066-smp"
 300           While optional, it is the preferred way to get access to
 301           the cpu-core power-domains.
 302
 303     required:
 304       - device_type
 305       - reg
 306       - compatible
 307
 308     dependencies:
 309       cpu-release-addr: [enable-method]
 310       rockchip,pmu: [enable-method]
 311
 312 required:
 313   - '#address-cells'
 314   - '#size-cells'
 315
 316 examples:
 317   - |
 318     cpus {
 319       #size-cells = <0>;
 320       #address-cells = <1>;
 321
 322       cpu@0 {
 323         device_type = "cpu";
 324         compatible = "arm,cortex-a15";
 325         reg = <0x0>;
 326       };
 327
 328       cpu@1 {
 329         device_type = "cpu";
 330         compatible = "arm,cortex-a15";
 331         reg = <0x1>;
 332       };
 333
 334       cpu@100 {
 335         device_type = "cpu";
 336         compatible = "arm,cortex-a7";
 337         reg = <0x100>;
 338       };
 339
 340       cpu@101 {
 341         device_type = "cpu";
 342         compatible = "arm,cortex-a7";
 343         reg = <0x101>;
 344       };
 345     };
 346
 347   - |
 348     // Example 2 (Cortex-A8 uniprocessor 32-bit system):
 349     cpus {
 350       #size-cells = <0>;
 351       #address-cells = <1>;
 352
 353       cpu@0 {
 354         device_type = "cpu";
 355         compatible = "arm,cortex-a8";
 356         reg = <0x0>;
 357       };
 358     };
 359
 360   - |
 361     // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 362     cpus {
 363       #size-cells = <0>;
 364       #address-cells = <1>;
 365
 366       cpu@0 {
 367         device_type = "cpu";
 368         compatible = "arm,arm926ej-s";
 369         reg = <0x0>;
 370       };
 371     };
 372
 373   - |
 374     //  Example 4 (ARM Cortex-A57 64-bit system):
 375     cpus {
 376       #size-cells = <0>;
 377       #address-cells = <2>;
 378
 379       cpu@0 {
 380         device_type = "cpu";
 381         compatible = "arm,cortex-a57";
 382         reg = <0x0 0x0>;
 383         enable-method = "spin-table";
 384         cpu-release-addr = <0 0x20000000>;
 385       };
 386
 387       cpu@1 {
 388         device_type = "cpu";
 389         compatible = "arm,cortex-a57";
 390         reg = <0x0 0x1>;
 391         enable-method = "spin-table";
 392         cpu-release-addr = <0 0x20000000>;
 393       };
 394
 395       cpu@100 {
 396         device_type = "cpu";
 397         compatible = "arm,cortex-a57";
 398         reg = <0x0 0x100>;
 399         enable-method = "spin-table";
 400         cpu-release-addr = <0 0x20000000>;
 401       };
 402
 403       cpu@101 {
 404         device_type = "cpu";
 405         compatible = "arm,cortex-a57";
 406         reg = <0x0 0x101>;
 407         enable-method = "spin-table";
 408         cpu-release-addr = <0 0x20000000>;
 409       };
 410
 411       cpu@10000 {
 412         device_type = "cpu";
 413         compatible = "arm,cortex-a57";
 414         reg = <0x0 0x10000>;
 415         enable-method = "spin-table";
 416         cpu-release-addr = <0 0x20000000>;
 417       };
 418
 419       cpu@10001 {
 420         device_type = "cpu";
 421         compatible = "arm,cortex-a57";
 422         reg = <0x0 0x10001>;
 423         enable-method = "spin-table";
 424         cpu-release-addr = <0 0x20000000>;
 425       };
 426
 427       cpu@10100 {
 428         device_type = "cpu";
 429         compatible = "arm,cortex-a57";
 430         reg = <0x0 0x10100>;
 431         enable-method = "spin-table";
 432         cpu-release-addr = <0 0x20000000>;
 433       };
 434
 435       cpu@10101 {
 436         device_type = "cpu";
 437         compatible = "arm,cortex-a57";
 438         reg = <0x0 0x10101>;
 439         enable-method = "spin-table";
 440         cpu-release-addr = <0 0x20000000>;
 441       };
 442
 443       cpu@100000000 {
 444         device_type = "cpu";
 445         compatible = "arm,cortex-a57";
 446         reg = <0x1 0x0>;
 447         enable-method = "spin-table";
 448         cpu-release-addr = <0 0x20000000>;
 449       };
 450
 451       cpu@100000001 {
 452         device_type = "cpu";
 453         compatible = "arm,cortex-a57";
 454         reg = <0x1 0x1>;
 455         enable-method = "spin-table";
 456         cpu-release-addr = <0 0x20000000>;
 457       };
 458
 459       cpu@100000100 {
 460         device_type = "cpu";
 461         compatible = "arm,cortex-a57";
 462         reg = <0x1 0x100>;
 463         enable-method = "spin-table";
 464         cpu-release-addr = <0 0x20000000>;
 465       };
 466
 467       cpu@100000101 {
 468         device_type = "cpu";
 469         compatible = "arm,cortex-a57";
 470         reg = <0x1 0x101>;
 471         enable-method = "spin-table";
 472         cpu-release-addr = <0 0x20000000>;
 473       };
 474
 475       cpu@100010000 {
 476         device_type = "cpu";
 477         compatible = "arm,cortex-a57";
 478         reg = <0x1 0x10000>;
 479         enable-method = "spin-table";
 480         cpu-release-addr = <0 0x20000000>;
 481       };
 482
 483       cpu@100010001 {
 484         device_type = "cpu";
 485         compatible = "arm,cortex-a57";
 486         reg = <0x1 0x10001>;
 487         enable-method = "spin-table";
 488         cpu-release-addr = <0 0x20000000>;
 489       };
 490
 491       cpu@100010100 {
 492         device_type = "cpu";
 493         compatible = "arm,cortex-a57";
 494         reg = <0x1 0x10100>;
 495         enable-method = "spin-table";
 496         cpu-release-addr = <0 0x20000000>;
 497       };
 498
 499       cpu@100010101 {
 500         device_type = "cpu";
 501         compatible = "arm,cortex-a57";
 502         reg = <0x1 0x10101>;
 503         enable-method = "spin-table";
 504         cpu-release-addr = <0 0x20000000>;
 505       };
 506     };
 507 ...