1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CPUs bindings
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
19 https://www.devicetree.org/specifications/
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
23 ================================
24 Convention used in this document
25 ================================
27 This document follows the conventions described in the Devicetree
28 Specification, with the addition:
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
33 =====================================
34 cpus and cpu node bindings definition
35 =====================================
37 The ARM architecture, in accordance with the Devicetree Specification,
38 requires the cpus and cpu nodes to be present and contain the properties
44 description: Container of cpu nodes
49 Definition depends on ARM architecture version and configuration:
51 On uniprocessor ARM architectures previous to v7
52 value must be 1, to enable a simple enumeration
53 scheme for processors that do not have a HW CPU
54 identification register.
55 On 32-bit ARM 11 MPcore, ARM v7 or later systems
56 value must be 1, that corresponds to CPUID/MPIDR
58 On ARM v8 64-bit systems value should be set to 2,
59 that corresponds to the MPIDR_EL1 register size.
60 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
61 in the system, #address-cells can be set to 1, since
62 MPIDR_EL1[63:32] bits are not used for CPUs
77 Usage and definition depend on ARM architecture version and
80 On uniprocessor ARM architectures previous to v7
81 this property is required and must be set to 0.
83 On ARM 11 MPcore based systems this property is
84 required and matches the CPUID[11:0] register bits.
86 Bits [11:0] in the reg cell must be set to
87 bits [11:0] in CPU ID register.
89 All other bits in the reg cell must be set to 0.
91 On 32-bit ARM v7 or later systems this property is
92 required and matches the CPU MPIDR[23:0] register
95 Bits [23:0] in the reg cell must be set to
98 All other bits in the reg cell must be set to 0.
100 On ARM v8 64-bit systems this property is required
101 and matches the MPIDR_EL1 register affinity bits.
103 * If cpus node's #address-cells property is set to 2
105 The first reg cell bits [7:0] must be set to
106 bits [39:32] of MPIDR_EL1.
108 The second reg cell bits [23:0] must be set to
109 bits [23:0] of MPIDR_EL1.
111 * If cpus node's #address-cells property is set to 1
113 The reg cell bits [23:0] must be set to bits [23:0]
116 All other bits in the reg cells must be set to 0.
151 - arm,armv8 # Only for s/w models
185 - nvidia,tegra132-denver
186 - nvidia,tegra186-denver
187 - nvidia,tegra194-carmel
195 - $ref: '/schemas/types.yaml#/definitions/string'
197 # On ARM v8 64-bit this property is required
201 # On ARM 32-bit systems this property is optional
204 - allwinner,sun6i-a31
205 - allwinner,sun8i-a23
206 - allwinner,sun9i-a80-smp
207 - allwinner,sun8i-a83t-smp
209 - amlogic,meson8b-smp
211 - brcm,bcm11351-cpu-method
217 - marvell,armada-375-smp
218 - marvell,armada-380-smp
219 - marvell,armada-390-smp
220 - marvell,armada-xp-smp
221 - marvell,98dx3236-smp
222 - mediatek,mt6589-smp
223 - mediatek,mt81xx-tz-smp
228 - renesas,r9a06g032-smp
229 - rockchip,rk3036-smp
230 - rockchip,rk3066-smp
234 $ref: '/schemas/types.yaml#/definitions/uint64'
237 Required for systems that have an "enable-method"
238 property value of "spin-table".
239 On ARM v8 64-bit systems must be a two cell
240 property identifying a 64-bit zero-initialised
244 $ref: '/schemas/types.yaml#/definitions/phandle-array'
246 List of phandles to idle state nodes supported
247 by this cpu (see ./idle-states.txt).
250 $ref: '/schemas/types.yaml#/definitions/uint32'
252 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
253 DMIPS/MHz, relative to highest capacity-dmips-mhz
256 dynamic-power-coefficient:
257 $ref: '/schemas/types.yaml#/definitions/uint32'
259 A u32 value that represents the running time dynamic
260 power coefficient in units of uW/MHz/V^2. The
261 coefficient can either be calculated from power
262 measurements or derived by analysis.
264 The dynamic power consumption of the CPU is
265 proportional to the square of the Voltage (V) and
266 the clock frequency (f). The coefficient is used to
267 calculate the dynamic power as below -
269 Pdyn = dynamic-power-coefficient * V^2 * f
271 where voltage is in V, frequency is in MHz.
274 $ref: '/schemas/types.yaml#/definitions/phandle'
276 Specifies the SAW* node associated with this CPU.
278 Required for systems that have an "enable-method" property
279 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
281 * arm/msm/qcom,saw2.txt
284 $ref: '/schemas/types.yaml#/definitions/phandle'
286 Specifies the ACC* node associated with this CPU.
288 Required for systems that have an "enable-method" property
289 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
291 * arm/msm/qcom,kpss-acc.txt
294 $ref: '/schemas/types.yaml#/definitions/phandle'
296 Specifies the syscon node controlling the cpu core power domains.
298 Optional for systems that have an "enable-method"
299 property value of "rockchip,rk3066-smp"
300 While optional, it is the preferred way to get access to
301 the cpu-core power-domains.
309 cpu-release-addr: [enable-method]
310 rockchip,pmu: [enable-method]
320 #address-cells = <1>;
324 compatible = "arm,cortex-a15";
330 compatible = "arm,cortex-a15";
336 compatible = "arm,cortex-a7";
342 compatible = "arm,cortex-a7";
348 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
351 #address-cells = <1>;
355 compatible = "arm,cortex-a8";
361 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
364 #address-cells = <1>;
368 compatible = "arm,arm926ej-s";
374 // Example 4 (ARM Cortex-A57 64-bit system):
377 #address-cells = <2>;
381 compatible = "arm,cortex-a57";
383 enable-method = "spin-table";
384 cpu-release-addr = <0 0x20000000>;
389 compatible = "arm,cortex-a57";
391 enable-method = "spin-table";
392 cpu-release-addr = <0 0x20000000>;
397 compatible = "arm,cortex-a57";
399 enable-method = "spin-table";
400 cpu-release-addr = <0 0x20000000>;
405 compatible = "arm,cortex-a57";
407 enable-method = "spin-table";
408 cpu-release-addr = <0 0x20000000>;
413 compatible = "arm,cortex-a57";
415 enable-method = "spin-table";
416 cpu-release-addr = <0 0x20000000>;
421 compatible = "arm,cortex-a57";
423 enable-method = "spin-table";
424 cpu-release-addr = <0 0x20000000>;
429 compatible = "arm,cortex-a57";
431 enable-method = "spin-table";
432 cpu-release-addr = <0 0x20000000>;
437 compatible = "arm,cortex-a57";
439 enable-method = "spin-table";
440 cpu-release-addr = <0 0x20000000>;
445 compatible = "arm,cortex-a57";
447 enable-method = "spin-table";
448 cpu-release-addr = <0 0x20000000>;
453 compatible = "arm,cortex-a57";
455 enable-method = "spin-table";
456 cpu-release-addr = <0 0x20000000>;
461 compatible = "arm,cortex-a57";
463 enable-method = "spin-table";
464 cpu-release-addr = <0 0x20000000>;
469 compatible = "arm,cortex-a57";
471 enable-method = "spin-table";
472 cpu-release-addr = <0 0x20000000>;
477 compatible = "arm,cortex-a57";
479 enable-method = "spin-table";
480 cpu-release-addr = <0 0x20000000>;
485 compatible = "arm,cortex-a57";
487 enable-method = "spin-table";
488 cpu-release-addr = <0 0x20000000>;
493 compatible = "arm,cortex-a57";
495 enable-method = "spin-table";
496 cpu-release-addr = <0 0x20000000>;
501 compatible = "arm,cortex-a57";
503 enable-method = "spin-table";
504 cpu-release-addr = <0 0x20000000>;