Documentation/devicetree/bindings/arm/cpus.txt

   1 =================
   2 ARM CPUs bindings
   3 =================
   4
   5 The device tree allows to describe the layout of CPUs in a system through
   6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
   7 defining properties for every cpu.
   8
   9 Bindings for CPU nodes follow the Devicetree Specification, available from:
  10
  11 https://www.devicetree.org/specifications/
  12
  13 with updates for 32-bit and 64-bit ARM systems provided in this document.
  14
  15 ================================
  16 Convention used in this document
  17 ================================
  18
  19 This document follows the conventions described in the Devicetree
  20 Specification, with the addition:
  21
  22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  23   the reg property contained in bits 7 down to 0
  24
  25 =====================================
  26 cpus and cpu node bindings definition
  27 =====================================
  28
  29 The ARM architecture, in accordance with the Devicetree Specification,
  30 requires the cpus and cpu nodes to be present and contain the properties
  31 described below.
  32
  33 - cpus node
  34
  35         Description: Container of cpu nodes
  36
  37         The node name must be "cpus".
  38
  39         A cpus node must define the following properties:
  40
  41         - #address-cells
  42                 Usage: required
  43                 Value type: <u32>
  44
  45                 Definition depends on ARM architecture version and
  46                 configuration:
  47
  48                         # On uniprocessor ARM architectures previous to v7
  49                           value must be 1, to enable a simple enumeration
  50                           scheme for processors that do not have a HW CPU
  51                           identification register.
  52                         # On 32-bit ARM 11 MPcore, ARM v7 or later systems
  53                           value must be 1, that corresponds to CPUID/MPIDR
  54                           registers sizes.
  55                         # On ARM v8 64-bit systems value should be set to 2,
  56                           that corresponds to the MPIDR_EL1 register size.
  57                           If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
  58                           in the system, #address-cells can be set to 1, since
  59                           MPIDR_EL1[63:32] bits are not used for CPUs
  60                           identification.
  61         - #size-cells
  62                 Usage: required
  63                 Value type: <u32>
  64                 Definition: must be set to 0
  65
  66 - cpu node
  67
  68         Description: Describes a CPU in an ARM based system
  69
  70         PROPERTIES
  71
  72         - device_type
  73                 Usage: required
  74                 Value type: <string>
  75                 Definition: must be "cpu"
  76         - reg
  77                 Usage and definition depend on ARM architecture version and
  78                 configuration:
  79
  80                         # On uniprocessor ARM architectures previous to v7
  81                           this property is required and must be set to 0.
  82
  83                         # On ARM 11 MPcore based systems this property is
  84                           required and matches the CPUID[11:0] register bits.
  85
  86                           Bits [11:0] in the reg cell must be set to
  87                           bits [11:0] in CPU ID register.
  88
  89                           All other bits in the reg cell must be set to 0.
  90
  91                         # On 32-bit ARM v7 or later systems this property is
  92                           required and matches the CPU MPIDR[23:0] register
  93                           bits.
  94
  95                           Bits [23:0] in the reg cell must be set to
  96                           bits [23:0] in MPIDR.
  97
  98                           All other bits in the reg cell must be set to 0.
  99
 100                         # On ARM v8 64-bit systems this property is required
 101                           and matches the MPIDR_EL1 register affinity bits.
 102
 103                           * If cpus node's #address-cells property is set to 2
 104
 105                             The first reg cell bits [7:0] must be set to
 106                             bits [39:32] of MPIDR_EL1.
 107
 108                             The second reg cell bits [23:0] must be set to
 109                             bits [23:0] of MPIDR_EL1.
 110
 111                           * If cpus node's #address-cells property is set to 1
 112
 113                             The reg cell bits [23:0] must be set to bits [23:0]
 114                             of MPIDR_EL1.
 115
 116                           All other bits in the reg cells must be set to 0.
 117
 118         - compatible:
 119                 Usage: required
 120                 Value type: <string>
 121                 Definition: should be one of:
 122                             "arm,arm710t"
 123                             "arm,arm720t"
 124                             "arm,arm740t"
 125                             "arm,arm7ej-s"
 126                             "arm,arm7tdmi"
 127                             "arm,arm7tdmi-s"
 128                             "arm,arm9es"
 129                             "arm,arm9ej-s"
 130                             "arm,arm920t"
 131                             "arm,arm922t"
 132                             "arm,arm925"
 133                             "arm,arm926e-s"
 134                             "arm,arm926ej-s"
 135                             "arm,arm940t"
 136                             "arm,arm946e-s"
 137                             "arm,arm966e-s"
 138                             "arm,arm968e-s"
 139                             "arm,arm9tdmi"
 140                             "arm,arm1020e"
 141                             "arm,arm1020t"
 142                             "arm,arm1022e"
 143                             "arm,arm1026ej-s"
 144                             "arm,arm1136j-s"
 145                             "arm,arm1136jf-s"
 146                             "arm,arm1156t2-s"
 147                             "arm,arm1156t2f-s"
 148                             "arm,arm1176jzf"
 149                             "arm,arm1176jz-s"
 150                             "arm,arm1176jzf-s"
 151                             "arm,arm11mpcore"
 152                             "arm,cortex-a5"
 153                             "arm,cortex-a7"
 154                             "arm,cortex-a8"
 155                             "arm,cortex-a9"
 156                             "arm,cortex-a12"
 157                             "arm,cortex-a15"
 158                             "arm,cortex-a17"
 159                             "arm,cortex-a53"
 160                             "arm,cortex-a57"
 161                             "arm,cortex-a72"
 162                             "arm,cortex-a73"
 163                             "arm,cortex-m0"
 164                             "arm,cortex-m0+"
 165                             "arm,cortex-m1"
 166                             "arm,cortex-m3"
 167                             "arm,cortex-m4"
 168                             "arm,cortex-r4"
 169                             "arm,cortex-r5"
 170                             "arm,cortex-r7"
 171                             "brcm,brahma-b15"
 172                             "brcm,brahma-b53"
 173                             "brcm,vulcan"
 174                             "cavium,thunder"
 175                             "cavium,thunder2"
 176                             "faraday,fa526"
 177                             "intel,sa110"
 178                             "intel,sa1100"
 179                             "marvell,feroceon"
 180                             "marvell,mohawk"
 181                             "marvell,pj4a"
 182                             "marvell,pj4b"
 183                             "marvell,sheeva-v5"
 184                             "nvidia,tegra132-denver"
 185                             "nvidia,tegra186-denver"
 186                             "qcom,krait"
 187                             "qcom,kryo"
 188                             "qcom,scorpion"
 189         - enable-method
 190                 Value type: <stringlist>
 191                 Usage and definition depend on ARM architecture version.
 192                         # On ARM v8 64-bit this property is required and must
 193                           be one of:
 194                              "psci"
 195                              "spin-table"
 196                         # On ARM 32-bit systems this property is optional and
 197                           can be one of:
 198                             "actions,s500-smp"
 199                             "allwinner,sun6i-a31"
 200                             "allwinner,sun8i-a23"
 201                             "amlogic,meson8-smp"
 202                             "amlogic,meson8b-smp"
 203                             "arm,realview-smp"
 204                             "brcm,bcm11351-cpu-method"
 205                             "brcm,bcm23550"
 206                             "brcm,bcm2836-smp"
 207                             "brcm,bcm-nsp-smp"
 208                             "brcm,brahma-b15"
 209                             "marvell,armada-375-smp"
 210                             "marvell,armada-380-smp"
 211                             "marvell,armada-390-smp"
 212                             "marvell,armada-xp-smp"
 213                             "marvell,98dx3236-smp"
 214                             "mediatek,mt6589-smp"
 215                             "mediatek,mt81xx-tz-smp"
 216                             "qcom,gcc-msm8660"
 217                             "qcom,kpss-acc-v1"
 218                             "qcom,kpss-acc-v2"
 219                             "renesas,apmu"
 220                             "rockchip,rk3036-smp"
 221                             "rockchip,rk3066-smp"
 222                             "ste,dbx500-smp"
 223
 224         - cpu-release-addr
 225                 Usage: required for systems that have an "enable-method"
 226                        property value of "spin-table".
 227                 Value type: <prop-encoded-array>
 228                 Definition:
 229                         # On ARM v8 64-bit systems must be a two cell
 230                           property identifying a 64-bit zero-initialised
 231                           memory location.
 232
 233         - qcom,saw
 234                 Usage: required for systems that have an "enable-method"
 235                        property value of "qcom,kpss-acc-v1" or
 236                        "qcom,kpss-acc-v2"
 237                 Value type: <phandle>
 238                 Definition: Specifies the SAW[1] node associated with this CPU.
 239
 240         - qcom,acc
 241                 Usage: required for systems that have an "enable-method"
 242                        property value of "qcom,kpss-acc-v1" or
 243                        "qcom,kpss-acc-v2"
 244                 Value type: <phandle>
 245                 Definition: Specifies the ACC[2] node associated with this CPU.
 246
 247         - cpu-idle-states
 248                 Usage: Optional
 249                 Value type: <prop-encoded-array>
 250                 Definition:
 251                         # List of phandles to idle state nodes supported
 252                           by this cpu [3].
 253
 254         - capacity-dmips-mhz
 255                 Usage: Optional
 256                 Value type: <u32>
 257                 Definition:
 258                         # u32 value representing CPU capacity [4] in
 259                           DMIPS/MHz, relative to highest capacity-dmips-mhz
 260                           in the system.
 261
 262         - rockchip,pmu
 263                 Usage: optional for systems that have an "enable-method"
 264                        property value of "rockchip,rk3066-smp"
 265                        While optional, it is the preferred way to get access to
 266                        the cpu-core power-domains.
 267                 Value type: <phandle>
 268                 Definition: Specifies the syscon node controlling the cpu core
 269                             power domains.
 270
 271         - dynamic-power-coefficient
 272                 Usage: optional
 273                 Value type: <prop-encoded-array>
 274                 Definition: A u32 value that represents the running time dynamic
 275                             power coefficient in units of mW/MHz/uV^2. The
 276                             coefficient can either be calculated from power
 277                             measurements or derived by analysis.
 278
 279                             The dynamic power consumption of the CPU  is
 280                             proportional to the square of the Voltage (V) and
 281                             the clock frequency (f). The coefficient is used to
 282                             calculate the dynamic power as below -
 283
 284                             Pdyn = dynamic-power-coefficient * V^2 * f
 285
 286                             where voltage is in uV, frequency is in MHz.
 287
 288 Example 1 (dual-cluster big.LITTLE system 32-bit):
 289
 290         cpus {
 291                 #size-cells = <0>;
 292                 #address-cells = <1>;
 293
 294                 cpu@0 {
 295                         device_type = "cpu";
 296                         compatible = "arm,cortex-a15";
 297                         reg = <0x0>;
 298                 };
 299
 300                 cpu@1 {
 301                         device_type = "cpu";
 302                         compatible = "arm,cortex-a15";
 303                         reg = <0x1>;
 304                 };
 305
 306                 cpu@100 {
 307                         device_type = "cpu";
 308                         compatible = "arm,cortex-a7";
 309                         reg = <0x100>;
 310                 };
 311
 312                 cpu@101 {
 313                         device_type = "cpu";
 314                         compatible = "arm,cortex-a7";
 315                         reg = <0x101>;
 316                 };
 317         };
 318
 319 Example 2 (Cortex-A8 uniprocessor 32-bit system):
 320
 321         cpus {
 322                 #size-cells = <0>;
 323                 #address-cells = <1>;
 324
 325                 cpu@0 {
 326                         device_type = "cpu";
 327                         compatible = "arm,cortex-a8";
 328                         reg = <0x0>;
 329                 };
 330         };
 331
 332 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 333
 334         cpus {
 335                 #size-cells = <0>;
 336                 #address-cells = <1>;
 337
 338                 cpu@0 {
 339                         device_type = "cpu";
 340                         compatible = "arm,arm926ej-s";
 341                         reg = <0x0>;
 342                 };
 343         };
 344
 345 Example 4 (ARM Cortex-A57 64-bit system):
 346
 347 cpus {
 348         #size-cells = <0>;
 349         #address-cells = <2>;
 350
 351         cpu@0 {
 352                 device_type = "cpu";
 353                 compatible = "arm,cortex-a57";
 354                 reg = <0x0 0x0>;
 355                 enable-method = "spin-table";
 356                 cpu-release-addr = <0 0x20000000>;
 357         };
 358
 359         cpu@1 {
 360                 device_type = "cpu";
 361                 compatible = "arm,cortex-a57";
 362                 reg = <0x0 0x1>;
 363                 enable-method = "spin-table";
 364                 cpu-release-addr = <0 0x20000000>;
 365         };
 366
 367         cpu@100 {
 368                 device_type = "cpu";
 369                 compatible = "arm,cortex-a57";
 370                 reg = <0x0 0x100>;
 371                 enable-method = "spin-table";
 372                 cpu-release-addr = <0 0x20000000>;
 373         };
 374
 375         cpu@101 {
 376                 device_type = "cpu";
 377                 compatible = "arm,cortex-a57";
 378                 reg = <0x0 0x101>;
 379                 enable-method = "spin-table";
 380                 cpu-release-addr = <0 0x20000000>;
 381         };
 382
 383         cpu@10000 {
 384                 device_type = "cpu";
 385                 compatible = "arm,cortex-a57";
 386                 reg = <0x0 0x10000>;
 387                 enable-method = "spin-table";
 388                 cpu-release-addr = <0 0x20000000>;
 389         };
 390
 391         cpu@10001 {
 392                 device_type = "cpu";
 393                 compatible = "arm,cortex-a57";
 394                 reg = <0x0 0x10001>;
 395                 enable-method = "spin-table";
 396                 cpu-release-addr = <0 0x20000000>;
 397         };
 398
 399         cpu@10100 {
 400                 device_type = "cpu";
 401                 compatible = "arm,cortex-a57";
 402                 reg = <0x0 0x10100>;
 403                 enable-method = "spin-table";
 404                 cpu-release-addr = <0 0x20000000>;
 405         };
 406
 407         cpu@10101 {
 408                 device_type = "cpu";
 409                 compatible = "arm,cortex-a57";
 410                 reg = <0x0 0x10101>;
 411                 enable-method = "spin-table";
 412                 cpu-release-addr = <0 0x20000000>;
 413         };
 414
 415         cpu@100000000 {
 416                 device_type = "cpu";
 417                 compatible = "arm,cortex-a57";
 418                 reg = <0x1 0x0>;
 419                 enable-method = "spin-table";
 420                 cpu-release-addr = <0 0x20000000>;
 421         };
 422
 423         cpu@100000001 {
 424                 device_type = "cpu";
 425                 compatible = "arm,cortex-a57";
 426                 reg = <0x1 0x1>;
 427                 enable-method = "spin-table";
 428                 cpu-release-addr = <0 0x20000000>;
 429         };
 430
 431         cpu@100000100 {
 432                 device_type = "cpu";
 433                 compatible = "arm,cortex-a57";
 434                 reg = <0x1 0x100>;
 435                 enable-method = "spin-table";
 436                 cpu-release-addr = <0 0x20000000>;
 437         };
 438
 439         cpu@100000101 {
 440                 device_type = "cpu";
 441                 compatible = "arm,cortex-a57";
 442                 reg = <0x1 0x101>;
 443                 enable-method = "spin-table";
 444                 cpu-release-addr = <0 0x20000000>;
 445         };
 446
 447         cpu@100010000 {
 448                 device_type = "cpu";
 449                 compatible = "arm,cortex-a57";
 450                 reg = <0x1 0x10000>;
 451                 enable-method = "spin-table";
 452                 cpu-release-addr = <0 0x20000000>;
 453         };
 454
 455         cpu@100010001 {
 456                 device_type = "cpu";
 457                 compatible = "arm,cortex-a57";
 458                 reg = <0x1 0x10001>;
 459                 enable-method = "spin-table";
 460                 cpu-release-addr = <0 0x20000000>;
 461         };
 462
 463         cpu@100010100 {
 464                 device_type = "cpu";
 465                 compatible = "arm,cortex-a57";
 466                 reg = <0x1 0x10100>;
 467                 enable-method = "spin-table";
 468                 cpu-release-addr = <0 0x20000000>;
 469         };
 470
 471         cpu@100010101 {
 472                 device_type = "cpu";
 473                 compatible = "arm,cortex-a57";
 474                 reg = <0x1 0x10101>;
 475                 enable-method = "spin-table";
 476                 cpu-release-addr = <0 0x20000000>;
 477         };
 478 };
 479
 480 --
 481 [1] arm/msm/qcom,saw2.txt
 482 [2] arm/msm/qcom,kpss-acc.txt
 483 [3] ARM Linux kernel documentation - idle states bindings
 484     Documentation/devicetree/bindings/arm/idle-states.txt
 485 [4] ARM Linux kernel documentation - cpu capacity bindings
 486     Documentation/devicetree/bindings/arm/cpu-capacity.txt