Documentation/devicetree/bindings/arm/cpus.txt

   1 =================
   2 ARM CPUs bindings
   3 =================
   4
   5 The device tree allows to describe the layout of CPUs in a system through
   6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
   7 defining properties for every cpu.
   8
   9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
  10
  11 https://www.power.org/documentation/epapr-version-1-1/
  12
  13 with updates for 32-bit and 64-bit ARM systems provided in this document.
  14
  15 ================================
  16 Convention used in this document
  17 ================================
  18
  19 This document follows the conventions described in the ePAPR v1.1, with
  20 the addition:
  21
  22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  23   the reg property contained in bits 7 down to 0
  24
  25 =====================================
  26 cpus and cpu node bindings definition
  27 =====================================
  28
  29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
  30 nodes to be present and contain the properties described below.
  31
  32 - cpus node
  33
  34         Description: Container of cpu nodes
  35
  36         The node name must be "cpus".
  37
  38         A cpus node must define the following properties:
  39
  40         - #address-cells
  41                 Usage: required
  42                 Value type: <u32>
  43
  44                 Definition depends on ARM architecture version and
  45                 configuration:
  46
  47                         # On uniprocessor ARM architectures previous to v7
  48                           value must be 1, to enable a simple enumeration
  49                           scheme for processors that do not have a HW CPU
  50                           identification register.
  51                         # On 32-bit ARM 11 MPcore, ARM v7 or later systems
  52                           value must be 1, that corresponds to CPUID/MPIDR
  53                           registers sizes.
  54                         # On ARM v8 64-bit systems value should be set to 2,
  55                           that corresponds to the MPIDR_EL1 register size.
  56                           If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
  57                           in the system, #address-cells can be set to 1, since
  58                           MPIDR_EL1[63:32] bits are not used for CPUs
  59                           identification.
  60         - #size-cells
  61                 Usage: required
  62                 Value type: <u32>
  63                 Definition: must be set to 0
  64
  65 - cpu node
  66
  67         Description: Describes a CPU in an ARM based system
  68
  69         PROPERTIES
  70
  71         - device_type
  72                 Usage: required
  73                 Value type: <string>
  74                 Definition: must be "cpu"
  75         - reg
  76                 Usage and definition depend on ARM architecture version and
  77                 configuration:
  78
  79                         # On uniprocessor ARM architectures previous to v7
  80                           this property is required and must be set to 0.
  81
  82                         # On ARM 11 MPcore based systems this property is
  83                           required and matches the CPUID[11:0] register bits.
  84
  85                           Bits [11:0] in the reg cell must be set to
  86                           bits [11:0] in CPU ID register.
  87
  88                           All other bits in the reg cell must be set to 0.
  89
  90                         # On 32-bit ARM v7 or later systems this property is
  91                           required and matches the CPU MPIDR[23:0] register
  92                           bits.
  93
  94                           Bits [23:0] in the reg cell must be set to
  95                           bits [23:0] in MPIDR.
  96
  97                           All other bits in the reg cell must be set to 0.
  98
  99                         # On ARM v8 64-bit systems this property is required
 100                           and matches the MPIDR_EL1 register affinity bits.
 101
 102                           * If cpus node's #address-cells property is set to 2
 103
 104                             The first reg cell bits [7:0] must be set to
 105                             bits [39:32] of MPIDR_EL1.
 106
 107                             The second reg cell bits [23:0] must be set to
 108                             bits [23:0] of MPIDR_EL1.
 109
 110                           * If cpus node's #address-cells property is set to 1
 111
 112                             The reg cell bits [23:0] must be set to bits [23:0]
 113                             of MPIDR_EL1.
 114
 115                           All other bits in the reg cells must be set to 0.
 116
 117         - compatible:
 118                 Usage: required
 119                 Value type: <string>
 120                 Definition: should be one of:
 121                             "arm,arm710t"
 122                             "arm,arm720t"
 123                             "arm,arm740t"
 124                             "arm,arm7ej-s"
 125                             "arm,arm7tdmi"
 126                             "arm,arm7tdmi-s"
 127                             "arm,arm9es"
 128                             "arm,arm9ej-s"
 129                             "arm,arm920t"
 130                             "arm,arm922t"
 131                             "arm,arm925"
 132                             "arm,arm926e-s"
 133                             "arm,arm926ej-s"
 134                             "arm,arm940t"
 135                             "arm,arm946e-s"
 136                             "arm,arm966e-s"
 137                             "arm,arm968e-s"
 138                             "arm,arm9tdmi"
 139                             "arm,arm1020e"
 140                             "arm,arm1020t"
 141                             "arm,arm1022e"
 142                             "arm,arm1026ej-s"
 143                             "arm,arm1136j-s"
 144                             "arm,arm1136jf-s"
 145                             "arm,arm1156t2-s"
 146                             "arm,arm1156t2f-s"
 147                             "arm,arm1176jzf"
 148                             "arm,arm1176jz-s"
 149                             "arm,arm1176jzf-s"
 150                             "arm,arm11mpcore"
 151                             "arm,cortex-a5"
 152                             "arm,cortex-a7"
 153                             "arm,cortex-a8"
 154                             "arm,cortex-a9"
 155                             "arm,cortex-a12"
 156                             "arm,cortex-a15"
 157                             "arm,cortex-a17"
 158                             "arm,cortex-a53"
 159                             "arm,cortex-a57"
 160                             "arm,cortex-a72"
 161                             "arm,cortex-m0"
 162                             "arm,cortex-m0+"
 163                             "arm,cortex-m1"
 164                             "arm,cortex-m3"
 165                             "arm,cortex-m4"
 166                             "arm,cortex-r4"
 167                             "arm,cortex-r5"
 168                             "arm,cortex-r7"
 169                             "brcm,brahma-b15"
 170                             "brcm,vulcan"
 171                             "cavium,thunder"
 172                             "faraday,fa526"
 173                             "intel,sa110"
 174                             "intel,sa1100"
 175                             "marvell,feroceon"
 176                             "marvell,mohawk"
 177                             "marvell,pj4a"
 178                             "marvell,pj4b"
 179                             "marvell,sheeva-v5"
 180                             "nvidia,tegra132-denver"
 181                             "qcom,krait"
 182                             "qcom,kryo"
 183                             "qcom,scorpion"
 184         - enable-method
 185                 Value type: <stringlist>
 186                 Usage and definition depend on ARM architecture version.
 187                         # On ARM v8 64-bit this property is required and must
 188                           be one of:
 189                              "psci"
 190                              "spin-table"
 191                         # On ARM 32-bit systems this property is optional and
 192                           can be one of:
 193                             "allwinner,sun6i-a31"
 194                             "allwinner,sun8i-a23"
 195                             "arm,realview-smp"
 196                             "brcm,bcm11351-cpu-method"
 197                             "brcm,bcm23550"
 198                             "brcm,bcm-nsp-smp"
 199                             "brcm,brahma-b15"
 200                             "marvell,armada-375-smp"
 201                             "marvell,armada-380-smp"
 202                             "marvell,armada-390-smp"
 203                             "marvell,armada-xp-smp"
 204                             "mediatek,mt6589-smp"
 205                             "mediatek,mt81xx-tz-smp"
 206                             "qcom,gcc-msm8660"
 207                             "qcom,kpss-acc-v1"
 208                             "qcom,kpss-acc-v2"
 209                             "renesas,apmu"
 210                             "rockchip,rk3036-smp"
 211                             "rockchip,rk3066-smp"
 212                             "ste,dbx500-smp"
 213
 214         - cpu-release-addr
 215                 Usage: required for systems that have an "enable-method"
 216                        property value of "spin-table".
 217                 Value type: <prop-encoded-array>
 218                 Definition:
 219                         # On ARM v8 64-bit systems must be a two cell
 220                           property identifying a 64-bit zero-initialised
 221                           memory location.
 222
 223         - qcom,saw
 224                 Usage: required for systems that have an "enable-method"
 225                        property value of "qcom,kpss-acc-v1" or
 226                        "qcom,kpss-acc-v2"
 227                 Value type: <phandle>
 228                 Definition: Specifies the SAW[1] node associated with this CPU.
 229
 230         - qcom,acc
 231                 Usage: required for systems that have an "enable-method"
 232                        property value of "qcom,kpss-acc-v1" or
 233                        "qcom,kpss-acc-v2"
 234                 Value type: <phandle>
 235                 Definition: Specifies the ACC[2] node associated with this CPU.
 236
 237         - cpu-idle-states
 238                 Usage: Optional
 239                 Value type: <prop-encoded-array>
 240                 Definition:
 241                         # List of phandles to idle state nodes supported
 242                           by this cpu [3].
 243
 244         - rockchip,pmu
 245                 Usage: optional for systems that have an "enable-method"
 246                        property value of "rockchip,rk3066-smp"
 247                        While optional, it is the preferred way to get access to
 248                        the cpu-core power-domains.
 249                 Value type: <phandle>
 250                 Definition: Specifies the syscon node controlling the cpu core
 251                             power domains.
 252
 253         - dynamic-power-coefficient
 254                 Usage: optional
 255                 Value type: <prop-encoded-array>
 256                 Definition: A u32 value that represents the running time dynamic
 257                             power coefficient in units of mW/MHz/uV^2. The
 258                             coefficient can either be calculated from power
 259                             measurements or derived by analysis.
 260
 261                             The dynamic power consumption of the CPU  is
 262                             proportional to the square of the Voltage (V) and
 263                             the clock frequency (f). The coefficient is used to
 264                             calculate the dynamic power as below -
 265
 266                             Pdyn = dynamic-power-coefficient * V^2 * f
 267
 268                             where voltage is in uV, frequency is in MHz.
 269
 270 Example 1 (dual-cluster big.LITTLE system 32-bit):
 271
 272         cpus {
 273                 #size-cells = <0>;
 274                 #address-cells = <1>;
 275
 276                 cpu@0 {
 277                         device_type = "cpu";
 278                         compatible = "arm,cortex-a15";
 279                         reg = <0x0>;
 280                 };
 281
 282                 cpu@1 {
 283                         device_type = "cpu";
 284                         compatible = "arm,cortex-a15";
 285                         reg = <0x1>;
 286                 };
 287
 288                 cpu@100 {
 289                         device_type = "cpu";
 290                         compatible = "arm,cortex-a7";
 291                         reg = <0x100>;
 292                 };
 293
 294                 cpu@101 {
 295                         device_type = "cpu";
 296                         compatible = "arm,cortex-a7";
 297                         reg = <0x101>;
 298                 };
 299         };
 300
 301 Example 2 (Cortex-A8 uniprocessor 32-bit system):
 302
 303         cpus {
 304                 #size-cells = <0>;
 305                 #address-cells = <1>;
 306
 307                 cpu@0 {
 308                         device_type = "cpu";
 309                         compatible = "arm,cortex-a8";
 310                         reg = <0x0>;
 311                 };
 312         };
 313
 314 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 315
 316         cpus {
 317                 #size-cells = <0>;
 318                 #address-cells = <1>;
 319
 320                 cpu@0 {
 321                         device_type = "cpu";
 322                         compatible = "arm,arm926ej-s";
 323                         reg = <0x0>;
 324                 };
 325         };
 326
 327 Example 4 (ARM Cortex-A57 64-bit system):
 328
 329 cpus {
 330         #size-cells = <0>;
 331         #address-cells = <2>;
 332
 333         cpu@0 {
 334                 device_type = "cpu";
 335                 compatible = "arm,cortex-a57";
 336                 reg = <0x0 0x0>;
 337                 enable-method = "spin-table";
 338                 cpu-release-addr = <0 0x20000000>;
 339         };
 340
 341         cpu@1 {
 342                 device_type = "cpu";
 343                 compatible = "arm,cortex-a57";
 344                 reg = <0x0 0x1>;
 345                 enable-method = "spin-table";
 346                 cpu-release-addr = <0 0x20000000>;
 347         };
 348
 349         cpu@100 {
 350                 device_type = "cpu";
 351                 compatible = "arm,cortex-a57";
 352                 reg = <0x0 0x100>;
 353                 enable-method = "spin-table";
 354                 cpu-release-addr = <0 0x20000000>;
 355         };
 356
 357         cpu@101 {
 358                 device_type = "cpu";
 359                 compatible = "arm,cortex-a57";
 360                 reg = <0x0 0x101>;
 361                 enable-method = "spin-table";
 362                 cpu-release-addr = <0 0x20000000>;
 363         };
 364
 365         cpu@10000 {
 366                 device_type = "cpu";
 367                 compatible = "arm,cortex-a57";
 368                 reg = <0x0 0x10000>;
 369                 enable-method = "spin-table";
 370                 cpu-release-addr = <0 0x20000000>;
 371         };
 372
 373         cpu@10001 {
 374                 device_type = "cpu";
 375                 compatible = "arm,cortex-a57";
 376                 reg = <0x0 0x10001>;
 377                 enable-method = "spin-table";
 378                 cpu-release-addr = <0 0x20000000>;
 379         };
 380
 381         cpu@10100 {
 382                 device_type = "cpu";
 383                 compatible = "arm,cortex-a57";
 384                 reg = <0x0 0x10100>;
 385                 enable-method = "spin-table";
 386                 cpu-release-addr = <0 0x20000000>;
 387         };
 388
 389         cpu@10101 {
 390                 device_type = "cpu";
 391                 compatible = "arm,cortex-a57";
 392                 reg = <0x0 0x10101>;
 393                 enable-method = "spin-table";
 394                 cpu-release-addr = <0 0x20000000>;
 395         };
 396
 397         cpu@100000000 {
 398                 device_type = "cpu";
 399                 compatible = "arm,cortex-a57";
 400                 reg = <0x1 0x0>;
 401                 enable-method = "spin-table";
 402                 cpu-release-addr = <0 0x20000000>;
 403         };
 404
 405         cpu@100000001 {
 406                 device_type = "cpu";
 407                 compatible = "arm,cortex-a57";
 408                 reg = <0x1 0x1>;
 409                 enable-method = "spin-table";
 410                 cpu-release-addr = <0 0x20000000>;
 411         };
 412
 413         cpu@100000100 {
 414                 device_type = "cpu";
 415                 compatible = "arm,cortex-a57";
 416                 reg = <0x1 0x100>;
 417                 enable-method = "spin-table";
 418                 cpu-release-addr = <0 0x20000000>;
 419         };
 420
 421         cpu@100000101 {
 422                 device_type = "cpu";
 423                 compatible = "arm,cortex-a57";
 424                 reg = <0x1 0x101>;
 425                 enable-method = "spin-table";
 426                 cpu-release-addr = <0 0x20000000>;
 427         };
 428
 429         cpu@100010000 {
 430                 device_type = "cpu";
 431                 compatible = "arm,cortex-a57";
 432                 reg = <0x1 0x10000>;
 433                 enable-method = "spin-table";
 434                 cpu-release-addr = <0 0x20000000>;
 435         };
 436
 437         cpu@100010001 {
 438                 device_type = "cpu";
 439                 compatible = "arm,cortex-a57";
 440                 reg = <0x1 0x10001>;
 441                 enable-method = "spin-table";
 442                 cpu-release-addr = <0 0x20000000>;
 443         };
 444
 445         cpu@100010100 {
 446                 device_type = "cpu";
 447                 compatible = "arm,cortex-a57";
 448                 reg = <0x1 0x10100>;
 449                 enable-method = "spin-table";
 450                 cpu-release-addr = <0 0x20000000>;
 451         };
 452
 453         cpu@100010101 {
 454                 device_type = "cpu";
 455                 compatible = "arm,cortex-a57";
 456                 reg = <0x1 0x10101>;
 457                 enable-method = "spin-table";
 458                 cpu-release-addr = <0 0x20000000>;
 459         };
 460 };
 461
 462 --
 463 [1] arm/msm/qcom,saw2.txt
 464 [2] arm/msm/qcom,kpss-acc.txt
 465 [3] ARM Linux kernel documentation - idle states bindings
 466     Documentation/devicetree/bindings/arm/idle-states.txt