Documentation/devicetree/bindings/arm/cpus.txt

   1 =================
   2 ARM CPUs bindings
   3 =================
   4
   5 The device tree allows to describe the layout of CPUs in a system through
   6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
   7 defining properties for every cpu.
   8
   9 Bindings for CPU nodes follow the Devicetree Specification, available from:
  10
  11 https://www.devicetree.org/specifications/
  12
  13 with updates for 32-bit and 64-bit ARM systems provided in this document.
  14
  15 ================================
  16 Convention used in this document
  17 ================================
  18
  19 This document follows the conventions described in the Devicetree
  20 Specification, with the addition:
  21
  22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  23   the reg property contained in bits 7 down to 0
  24
  25 =====================================
  26 cpus and cpu node bindings definition
  27 =====================================
  28
  29 The ARM architecture, in accordance with the Devicetree Specification,
  30 requires the cpus and cpu nodes to be present and contain the properties
  31 described below.
  32
  33 - cpus node
  34
  35         Description: Container of cpu nodes
  36
  37         The node name must be "cpus".
  38
  39         A cpus node must define the following properties:
  40
  41         - #address-cells
  42                 Usage: required
  43                 Value type: <u32>
  44
  45                 Definition depends on ARM architecture version and
  46                 configuration:
  47
  48                         # On uniprocessor ARM architectures previous to v7
  49                           value must be 1, to enable a simple enumeration
  50                           scheme for processors that do not have a HW CPU
  51                           identification register.
  52                         # On 32-bit ARM 11 MPcore, ARM v7 or later systems
  53                           value must be 1, that corresponds to CPUID/MPIDR
  54                           registers sizes.
  55                         # On ARM v8 64-bit systems value should be set to 2,
  56                           that corresponds to the MPIDR_EL1 register size.
  57                           If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
  58                           in the system, #address-cells can be set to 1, since
  59                           MPIDR_EL1[63:32] bits are not used for CPUs
  60                           identification.
  61         - #size-cells
  62                 Usage: required
  63                 Value type: <u32>
  64                 Definition: must be set to 0
  65
  66 - cpu node
  67
  68         Description: Describes a CPU in an ARM based system
  69
  70         PROPERTIES
  71
  72         - device_type
  73                 Usage: required
  74                 Value type: <string>
  75                 Definition: must be "cpu"
  76         - reg
  77                 Usage and definition depend on ARM architecture version and
  78                 configuration:
  79
  80                         # On uniprocessor ARM architectures previous to v7
  81                           this property is required and must be set to 0.
  82
  83                         # On ARM 11 MPcore based systems this property is
  84                           required and matches the CPUID[11:0] register bits.
  85
  86                           Bits [11:0] in the reg cell must be set to
  87                           bits [11:0] in CPU ID register.
  88
  89                           All other bits in the reg cell must be set to 0.
  90
  91                         # On 32-bit ARM v7 or later systems this property is
  92                           required and matches the CPU MPIDR[23:0] register
  93                           bits.
  94
  95                           Bits [23:0] in the reg cell must be set to
  96                           bits [23:0] in MPIDR.
  97
  98                           All other bits in the reg cell must be set to 0.
  99
 100                         # On ARM v8 64-bit systems this property is required
 101                           and matches the MPIDR_EL1 register affinity bits.
 102
 103                           * If cpus node's #address-cells property is set to 2
 104
 105                             The first reg cell bits [7:0] must be set to
 106                             bits [39:32] of MPIDR_EL1.
 107
 108                             The second reg cell bits [23:0] must be set to
 109                             bits [23:0] of MPIDR_EL1.
 110
 111                           * If cpus node's #address-cells property is set to 1
 112
 113                             The reg cell bits [23:0] must be set to bits [23:0]
 114                             of MPIDR_EL1.
 115
 116                           All other bits in the reg cells must be set to 0.
 117
 118         - compatible:
 119                 Usage: required
 120                 Value type: <string>
 121                 Definition: should be one of:
 122                             "arm,arm710t"
 123                             "arm,arm720t"
 124                             "arm,arm740t"
 125                             "arm,arm7ej-s"
 126                             "arm,arm7tdmi"
 127                             "arm,arm7tdmi-s"
 128                             "arm,arm9es"
 129                             "arm,arm9ej-s"
 130                             "arm,arm920t"
 131                             "arm,arm922t"
 132                             "arm,arm925"
 133                             "arm,arm926e-s"
 134                             "arm,arm926ej-s"
 135                             "arm,arm940t"
 136                             "arm,arm946e-s"
 137                             "arm,arm966e-s"
 138                             "arm,arm968e-s"
 139                             "arm,arm9tdmi"
 140                             "arm,arm1020e"
 141                             "arm,arm1020t"
 142                             "arm,arm1022e"
 143                             "arm,arm1026ej-s"
 144                             "arm,arm1136j-s"
 145                             "arm,arm1136jf-s"
 146                             "arm,arm1156t2-s"
 147                             "arm,arm1156t2f-s"
 148                             "arm,arm1176jzf"
 149                             "arm,arm1176jz-s"
 150                             "arm,arm1176jzf-s"
 151                             "arm,arm11mpcore"
 152                             "arm,cortex-a5"
 153                             "arm,cortex-a7"
 154                             "arm,cortex-a8"
 155                             "arm,cortex-a9"
 156                             "arm,cortex-a12"
 157                             "arm,cortex-a15"
 158                             "arm,cortex-a17"
 159                             "arm,cortex-a53"
 160                             "arm,cortex-a57"
 161                             "arm,cortex-a72"
 162                             "arm,cortex-a73"
 163                             "arm,cortex-m0"
 164                             "arm,cortex-m0+"
 165                             "arm,cortex-m1"
 166                             "arm,cortex-m3"
 167                             "arm,cortex-m4"
 168                             "arm,cortex-r4"
 169                             "arm,cortex-r5"
 170                             "arm,cortex-r7"
 171                             "brcm,brahma-b15"
 172                             "brcm,vulcan"
 173                             "cavium,thunder"
 174                             "cavium,thunder2"
 175                             "faraday,fa526"
 176                             "intel,sa110"
 177                             "intel,sa1100"
 178                             "marvell,feroceon"
 179                             "marvell,mohawk"
 180                             "marvell,pj4a"
 181                             "marvell,pj4b"
 182                             "marvell,sheeva-v5"
 183                             "nvidia,tegra132-denver"
 184                             "nvidia,tegra186-denver"
 185                             "qcom,krait"
 186                             "qcom,kryo"
 187                             "qcom,scorpion"
 188         - enable-method
 189                 Value type: <stringlist>
 190                 Usage and definition depend on ARM architecture version.
 191                         # On ARM v8 64-bit this property is required and must
 192                           be one of:
 193                              "psci"
 194                              "spin-table"
 195                         # On ARM 32-bit systems this property is optional and
 196                           can be one of:
 197                             "actions,s500-smp"
 198                             "allwinner,sun6i-a31"
 199                             "allwinner,sun8i-a23"
 200                             "amlogic,meson8-smp"
 201                             "amlogic,meson8b-smp"
 202                             "arm,realview-smp"
 203                             "brcm,bcm11351-cpu-method"
 204                             "brcm,bcm23550"
 205                             "brcm,bcm2836-smp"
 206                             "brcm,bcm-nsp-smp"
 207                             "brcm,brahma-b15"
 208                             "marvell,armada-375-smp"
 209                             "marvell,armada-380-smp"
 210                             "marvell,armada-390-smp"
 211                             "marvell,armada-xp-smp"
 212                             "marvell,98dx3236-smp"
 213                             "mediatek,mt6589-smp"
 214                             "mediatek,mt81xx-tz-smp"
 215                             "qcom,gcc-msm8660"
 216                             "qcom,kpss-acc-v1"
 217                             "qcom,kpss-acc-v2"
 218                             "renesas,apmu"
 219                             "rockchip,rk3036-smp"
 220                             "rockchip,rk3066-smp"
 221                             "ste,dbx500-smp"
 222
 223         - cpu-release-addr
 224                 Usage: required for systems that have an "enable-method"
 225                        property value of "spin-table".
 226                 Value type: <prop-encoded-array>
 227                 Definition:
 228                         # On ARM v8 64-bit systems must be a two cell
 229                           property identifying a 64-bit zero-initialised
 230                           memory location.
 231
 232         - qcom,saw
 233                 Usage: required for systems that have an "enable-method"
 234                        property value of "qcom,kpss-acc-v1" or
 235                        "qcom,kpss-acc-v2"
 236                 Value type: <phandle>
 237                 Definition: Specifies the SAW[1] node associated with this CPU.
 238
 239         - qcom,acc
 240                 Usage: required for systems that have an "enable-method"
 241                        property value of "qcom,kpss-acc-v1" or
 242                        "qcom,kpss-acc-v2"
 243                 Value type: <phandle>
 244                 Definition: Specifies the ACC[2] node associated with this CPU.
 245
 246         - cpu-idle-states
 247                 Usage: Optional
 248                 Value type: <prop-encoded-array>
 249                 Definition:
 250                         # List of phandles to idle state nodes supported
 251                           by this cpu [3].
 252
 253         - capacity-dmips-mhz
 254                 Usage: Optional
 255                 Value type: <u32>
 256                 Definition:
 257                         # u32 value representing CPU capacity [4] in
 258                           DMIPS/MHz, relative to highest capacity-dmips-mhz
 259                           in the system.
 260
 261         - rockchip,pmu
 262                 Usage: optional for systems that have an "enable-method"
 263                        property value of "rockchip,rk3066-smp"
 264                        While optional, it is the preferred way to get access to
 265                        the cpu-core power-domains.
 266                 Value type: <phandle>
 267                 Definition: Specifies the syscon node controlling the cpu core
 268                             power domains.
 269
 270         - dynamic-power-coefficient
 271                 Usage: optional
 272                 Value type: <prop-encoded-array>
 273                 Definition: A u32 value that represents the running time dynamic
 274                             power coefficient in units of mW/MHz/uV^2. The
 275                             coefficient can either be calculated from power
 276                             measurements or derived by analysis.
 277
 278                             The dynamic power consumption of the CPU  is
 279                             proportional to the square of the Voltage (V) and
 280                             the clock frequency (f). The coefficient is used to
 281                             calculate the dynamic power as below -
 282
 283                             Pdyn = dynamic-power-coefficient * V^2 * f
 284
 285                             where voltage is in uV, frequency is in MHz.
 286
 287 Example 1 (dual-cluster big.LITTLE system 32-bit):
 288
 289         cpus {
 290                 #size-cells = <0>;
 291                 #address-cells = <1>;
 292
 293                 cpu@0 {
 294                         device_type = "cpu";
 295                         compatible = "arm,cortex-a15";
 296                         reg = <0x0>;
 297                 };
 298
 299                 cpu@1 {
 300                         device_type = "cpu";
 301                         compatible = "arm,cortex-a15";
 302                         reg = <0x1>;
 303                 };
 304
 305                 cpu@100 {
 306                         device_type = "cpu";
 307                         compatible = "arm,cortex-a7";
 308                         reg = <0x100>;
 309                 };
 310
 311                 cpu@101 {
 312                         device_type = "cpu";
 313                         compatible = "arm,cortex-a7";
 314                         reg = <0x101>;
 315                 };
 316         };
 317
 318 Example 2 (Cortex-A8 uniprocessor 32-bit system):
 319
 320         cpus {
 321                 #size-cells = <0>;
 322                 #address-cells = <1>;
 323
 324                 cpu@0 {
 325                         device_type = "cpu";
 326                         compatible = "arm,cortex-a8";
 327                         reg = <0x0>;
 328                 };
 329         };
 330
 331 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 332
 333         cpus {
 334                 #size-cells = <0>;
 335                 #address-cells = <1>;
 336
 337                 cpu@0 {
 338                         device_type = "cpu";
 339                         compatible = "arm,arm926ej-s";
 340                         reg = <0x0>;
 341                 };
 342         };
 343
 344 Example 4 (ARM Cortex-A57 64-bit system):
 345
 346 cpus {
 347         #size-cells = <0>;
 348         #address-cells = <2>;
 349
 350         cpu@0 {
 351                 device_type = "cpu";
 352                 compatible = "arm,cortex-a57";
 353                 reg = <0x0 0x0>;
 354                 enable-method = "spin-table";
 355                 cpu-release-addr = <0 0x20000000>;
 356         };
 357
 358         cpu@1 {
 359                 device_type = "cpu";
 360                 compatible = "arm,cortex-a57";
 361                 reg = <0x0 0x1>;
 362                 enable-method = "spin-table";
 363                 cpu-release-addr = <0 0x20000000>;
 364         };
 365
 366         cpu@100 {
 367                 device_type = "cpu";
 368                 compatible = "arm,cortex-a57";
 369                 reg = <0x0 0x100>;
 370                 enable-method = "spin-table";
 371                 cpu-release-addr = <0 0x20000000>;
 372         };
 373
 374         cpu@101 {
 375                 device_type = "cpu";
 376                 compatible = "arm,cortex-a57";
 377                 reg = <0x0 0x101>;
 378                 enable-method = "spin-table";
 379                 cpu-release-addr = <0 0x20000000>;
 380         };
 381
 382         cpu@10000 {
 383                 device_type = "cpu";
 384                 compatible = "arm,cortex-a57";
 385                 reg = <0x0 0x10000>;
 386                 enable-method = "spin-table";
 387                 cpu-release-addr = <0 0x20000000>;
 388         };
 389
 390         cpu@10001 {
 391                 device_type = "cpu";
 392                 compatible = "arm,cortex-a57";
 393                 reg = <0x0 0x10001>;
 394                 enable-method = "spin-table";
 395                 cpu-release-addr = <0 0x20000000>;
 396         };
 397
 398         cpu@10100 {
 399                 device_type = "cpu";
 400                 compatible = "arm,cortex-a57";
 401                 reg = <0x0 0x10100>;
 402                 enable-method = "spin-table";
 403                 cpu-release-addr = <0 0x20000000>;
 404         };
 405
 406         cpu@10101 {
 407                 device_type = "cpu";
 408                 compatible = "arm,cortex-a57";
 409                 reg = <0x0 0x10101>;
 410                 enable-method = "spin-table";
 411                 cpu-release-addr = <0 0x20000000>;
 412         };
 413
 414         cpu@100000000 {
 415                 device_type = "cpu";
 416                 compatible = "arm,cortex-a57";
 417                 reg = <0x1 0x0>;
 418                 enable-method = "spin-table";
 419                 cpu-release-addr = <0 0x20000000>;
 420         };
 421
 422         cpu@100000001 {
 423                 device_type = "cpu";
 424                 compatible = "arm,cortex-a57";
 425                 reg = <0x1 0x1>;
 426                 enable-method = "spin-table";
 427                 cpu-release-addr = <0 0x20000000>;
 428         };
 429
 430         cpu@100000100 {
 431                 device_type = "cpu";
 432                 compatible = "arm,cortex-a57";
 433                 reg = <0x1 0x100>;
 434                 enable-method = "spin-table";
 435                 cpu-release-addr = <0 0x20000000>;
 436         };
 437
 438         cpu@100000101 {
 439                 device_type = "cpu";
 440                 compatible = "arm,cortex-a57";
 441                 reg = <0x1 0x101>;
 442                 enable-method = "spin-table";
 443                 cpu-release-addr = <0 0x20000000>;
 444         };
 445
 446         cpu@100010000 {
 447                 device_type = "cpu";
 448                 compatible = "arm,cortex-a57";
 449                 reg = <0x1 0x10000>;
 450                 enable-method = "spin-table";
 451                 cpu-release-addr = <0 0x20000000>;
 452         };
 453
 454         cpu@100010001 {
 455                 device_type = "cpu";
 456                 compatible = "arm,cortex-a57";
 457                 reg = <0x1 0x10001>;
 458                 enable-method = "spin-table";
 459                 cpu-release-addr = <0 0x20000000>;
 460         };
 461
 462         cpu@100010100 {
 463                 device_type = "cpu";
 464                 compatible = "arm,cortex-a57";
 465                 reg = <0x1 0x10100>;
 466                 enable-method = "spin-table";
 467                 cpu-release-addr = <0 0x20000000>;
 468         };
 469
 470         cpu@100010101 {
 471                 device_type = "cpu";
 472                 compatible = "arm,cortex-a57";
 473                 reg = <0x1 0x10101>;
 474                 enable-method = "spin-table";
 475                 cpu-release-addr = <0 0x20000000>;
 476         };
 477 };
 478
 479 --
 480 [1] arm/msm/qcom,saw2.txt
 481 [2] arm/msm/qcom,kpss-acc.txt
 482 [3] ARM Linux kernel documentation - idle states bindings
 483     Documentation/devicetree/bindings/arm/idle-states.txt
 484 [4] ARM Linux kernel documentation - cpu capacity bindings
 485     Documentation/devicetree/bindings/arm/cpu-capacity.txt