5 The device tree allows to describe the layout of CPUs in a system through
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the Devicetree Specification, available from:
11 https://www.devicetree.org/specifications/
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
15 ================================
16 Convention used in this document
17 ================================
19 This document follows the conventions described in the Devicetree
20 Specification, with the addition:
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
23 the reg property contained in bits 7 down to 0
25 =====================================
26 cpus and cpu node bindings definition
27 =====================================
29 The ARM architecture, in accordance with the Devicetree Specification,
30 requires the cpus and cpu nodes to be present and contain the properties
35 Description: Container of cpu nodes
37 The node name must be "cpus".
39 A cpus node must define the following properties:
45 Definition depends on ARM architecture version and
48 # On uniprocessor ARM architectures previous to v7
49 value must be 1, to enable a simple enumeration
50 scheme for processors that do not have a HW CPU
51 identification register.
52 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
53 value must be 1, that corresponds to CPUID/MPIDR
55 # On ARM v8 64-bit systems value should be set to 2,
56 that corresponds to the MPIDR_EL1 register size.
57 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
58 in the system, #address-cells can be set to 1, since
59 MPIDR_EL1[63:32] bits are not used for CPUs
64 Definition: must be set to 0
68 Description: Describes a CPU in an ARM based system
75 Definition: must be "cpu"
77 Usage and definition depend on ARM architecture version and
80 # On uniprocessor ARM architectures previous to v7
81 this property is required and must be set to 0.
83 # On ARM 11 MPcore based systems this property is
84 required and matches the CPUID[11:0] register bits.
86 Bits [11:0] in the reg cell must be set to
87 bits [11:0] in CPU ID register.
89 All other bits in the reg cell must be set to 0.
91 # On 32-bit ARM v7 or later systems this property is
92 required and matches the CPU MPIDR[23:0] register
95 Bits [23:0] in the reg cell must be set to
98 All other bits in the reg cell must be set to 0.
100 # On ARM v8 64-bit systems this property is required
101 and matches the MPIDR_EL1 register affinity bits.
103 * If cpus node's #address-cells property is set to 2
105 The first reg cell bits [7:0] must be set to
106 bits [39:32] of MPIDR_EL1.
108 The second reg cell bits [23:0] must be set to
109 bits [23:0] of MPIDR_EL1.
111 * If cpus node's #address-cells property is set to 1
113 The reg cell bits [23:0] must be set to bits [23:0]
116 All other bits in the reg cells must be set to 0.
121 Definition: should be one of:
183 "nvidia,tegra132-denver"
184 "nvidia,tegra186-denver"
189 Value type: <stringlist>
190 Usage and definition depend on ARM architecture version.
191 # On ARM v8 64-bit this property is required and must
195 # On ARM 32-bit systems this property is optional and
198 "allwinner,sun6i-a31"
199 "allwinner,sun8i-a23"
201 "amlogic,meson8b-smp"
203 "brcm,bcm11351-cpu-method"
208 "marvell,armada-375-smp"
209 "marvell,armada-380-smp"
210 "marvell,armada-390-smp"
211 "marvell,armada-xp-smp"
212 "marvell,98dx3236-smp"
213 "mediatek,mt6589-smp"
214 "mediatek,mt81xx-tz-smp"
219 "rockchip,rk3036-smp"
220 "rockchip,rk3066-smp"
224 Usage: required for systems that have an "enable-method"
225 property value of "spin-table".
226 Value type: <prop-encoded-array>
228 # On ARM v8 64-bit systems must be a two cell
229 property identifying a 64-bit zero-initialised
233 Usage: required for systems that have an "enable-method"
234 property value of "qcom,kpss-acc-v1" or
236 Value type: <phandle>
237 Definition: Specifies the SAW[1] node associated with this CPU.
240 Usage: required for systems that have an "enable-method"
241 property value of "qcom,kpss-acc-v1" or
243 Value type: <phandle>
244 Definition: Specifies the ACC[2] node associated with this CPU.
248 Value type: <prop-encoded-array>
250 # List of phandles to idle state nodes supported
257 # u32 value representing CPU capacity [4] in
258 DMIPS/MHz, relative to highest capacity-dmips-mhz
262 Usage: optional for systems that have an "enable-method"
263 property value of "rockchip,rk3066-smp"
264 While optional, it is the preferred way to get access to
265 the cpu-core power-domains.
266 Value type: <phandle>
267 Definition: Specifies the syscon node controlling the cpu core
270 - dynamic-power-coefficient
272 Value type: <prop-encoded-array>
273 Definition: A u32 value that represents the running time dynamic
274 power coefficient in units of mW/MHz/uV^2. The
275 coefficient can either be calculated from power
276 measurements or derived by analysis.
278 The dynamic power consumption of the CPU is
279 proportional to the square of the Voltage (V) and
280 the clock frequency (f). The coefficient is used to
281 calculate the dynamic power as below -
283 Pdyn = dynamic-power-coefficient * V^2 * f
285 where voltage is in uV, frequency is in MHz.
287 Example 1 (dual-cluster big.LITTLE system 32-bit):
291 #address-cells = <1>;
295 compatible = "arm,cortex-a15";
301 compatible = "arm,cortex-a15";
307 compatible = "arm,cortex-a7";
313 compatible = "arm,cortex-a7";
318 Example 2 (Cortex-A8 uniprocessor 32-bit system):
322 #address-cells = <1>;
326 compatible = "arm,cortex-a8";
331 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
335 #address-cells = <1>;
339 compatible = "arm,arm926ej-s";
344 Example 4 (ARM Cortex-A57 64-bit system):
348 #address-cells = <2>;
352 compatible = "arm,cortex-a57";
354 enable-method = "spin-table";
355 cpu-release-addr = <0 0x20000000>;
360 compatible = "arm,cortex-a57";
362 enable-method = "spin-table";
363 cpu-release-addr = <0 0x20000000>;
368 compatible = "arm,cortex-a57";
370 enable-method = "spin-table";
371 cpu-release-addr = <0 0x20000000>;
376 compatible = "arm,cortex-a57";
378 enable-method = "spin-table";
379 cpu-release-addr = <0 0x20000000>;
384 compatible = "arm,cortex-a57";
386 enable-method = "spin-table";
387 cpu-release-addr = <0 0x20000000>;
392 compatible = "arm,cortex-a57";
394 enable-method = "spin-table";
395 cpu-release-addr = <0 0x20000000>;
400 compatible = "arm,cortex-a57";
402 enable-method = "spin-table";
403 cpu-release-addr = <0 0x20000000>;
408 compatible = "arm,cortex-a57";
410 enable-method = "spin-table";
411 cpu-release-addr = <0 0x20000000>;
416 compatible = "arm,cortex-a57";
418 enable-method = "spin-table";
419 cpu-release-addr = <0 0x20000000>;
424 compatible = "arm,cortex-a57";
426 enable-method = "spin-table";
427 cpu-release-addr = <0 0x20000000>;
432 compatible = "arm,cortex-a57";
434 enable-method = "spin-table";
435 cpu-release-addr = <0 0x20000000>;
440 compatible = "arm,cortex-a57";
442 enable-method = "spin-table";
443 cpu-release-addr = <0 0x20000000>;
448 compatible = "arm,cortex-a57";
450 enable-method = "spin-table";
451 cpu-release-addr = <0 0x20000000>;
456 compatible = "arm,cortex-a57";
458 enable-method = "spin-table";
459 cpu-release-addr = <0 0x20000000>;
464 compatible = "arm,cortex-a57";
466 enable-method = "spin-table";
467 cpu-release-addr = <0 0x20000000>;
472 compatible = "arm,cortex-a57";
474 enable-method = "spin-table";
475 cpu-release-addr = <0 0x20000000>;
480 [1] arm/msm/qcom,saw2.txt
481 [2] arm/msm/qcom,kpss-acc.txt
482 [3] ARM Linux kernel documentation - idle states bindings
483 Documentation/devicetree/bindings/arm/idle-states.txt
484 [4] ARM Linux kernel documentation - cpu capacity bindings
485 Documentation/devicetree/bindings/arm/cpu-capacity.txt