Documentation/devicetree/bindings/arm/cpus.txt

   1 =================
   2 ARM CPUs bindings
   3 =================
   4
   5 The device tree allows to describe the layout of CPUs in a system through
   6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
   7 defining properties for every cpu.
   8
   9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
  10
  11 https://www.power.org/documentation/epapr-version-1-1/
  12
  13 with updates for 32-bit and 64-bit ARM systems provided in this document.
  14
  15 ================================
  16 Convention used in this document
  17 ================================
  18
  19 This document follows the conventions described in the ePAPR v1.1, with
  20 the addition:
  21
  22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  23   the reg property contained in bits 7 down to 0
  24
  25 =====================================
  26 cpus and cpu node bindings definition
  27 =====================================
  28
  29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
  30 nodes to be present and contain the properties described below.
  31
  32 - cpus node
  33
  34         Description: Container of cpu nodes
  35
  36         The node name must be "cpus".
  37
  38         A cpus node must define the following properties:
  39
  40         - #address-cells
  41                 Usage: required
  42                 Value type: <u32>
  43
  44                 Definition depends on ARM architecture version and
  45                 configuration:
  46
  47                         # On uniprocessor ARM architectures previous to v7
  48                           value must be 1, to enable a simple enumeration
  49                           scheme for processors that do not have a HW CPU
  50                           identification register.
  51                         # On 32-bit ARM 11 MPcore, ARM v7 or later systems
  52                           value must be 1, that corresponds to CPUID/MPIDR
  53                           registers sizes.
  54                         # On ARM v8 64-bit systems value should be set to 2,
  55                           that corresponds to the MPIDR_EL1 register size.
  56                           If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
  57                           in the system, #address-cells can be set to 1, since
  58                           MPIDR_EL1[63:32] bits are not used for CPUs
  59                           identification.
  60         - #size-cells
  61                 Usage: required
  62                 Value type: <u32>
  63                 Definition: must be set to 0
  64
  65 - cpu node
  66
  67         Description: Describes a CPU in an ARM based system
  68
  69         PROPERTIES
  70
  71         - device_type
  72                 Usage: required
  73                 Value type: <string>
  74                 Definition: must be "cpu"
  75         - reg
  76                 Usage and definition depend on ARM architecture version and
  77                 configuration:
  78
  79                         # On uniprocessor ARM architectures previous to v7
  80                           this property is required and must be set to 0.
  81
  82                         # On ARM 11 MPcore based systems this property is
  83                           required and matches the CPUID[11:0] register bits.
  84
  85                           Bits [11:0] in the reg cell must be set to
  86                           bits [11:0] in CPU ID register.
  87
  88                           All other bits in the reg cell must be set to 0.
  89
  90                         # On 32-bit ARM v7 or later systems this property is
  91                           required and matches the CPU MPIDR[23:0] register
  92                           bits.
  93
  94                           Bits [23:0] in the reg cell must be set to
  95                           bits [23:0] in MPIDR.
  96
  97                           All other bits in the reg cell must be set to 0.
  98
  99                         # On ARM v8 64-bit systems this property is required
 100                           and matches the MPIDR_EL1 register affinity bits.
 101
 102                           * If cpus node's #address-cells property is set to 2
 103
 104                             The first reg cell bits [7:0] must be set to
 105                             bits [39:32] of MPIDR_EL1.
 106
 107                             The second reg cell bits [23:0] must be set to
 108                             bits [23:0] of MPIDR_EL1.
 109
 110                           * If cpus node's #address-cells property is set to 1
 111
 112                             The reg cell bits [23:0] must be set to bits [23:0]
 113                             of MPIDR_EL1.
 114
 115                           All other bits in the reg cells must be set to 0.
 116
 117         - compatible:
 118                 Usage: required
 119                 Value type: <string>
 120                 Definition: should be one of:
 121                             "arm,arm710t"
 122                             "arm,arm720t"
 123                             "arm,arm740t"
 124                             "arm,arm7ej-s"
 125                             "arm,arm7tdmi"
 126                             "arm,arm7tdmi-s"
 127                             "arm,arm9es"
 128                             "arm,arm9ej-s"
 129                             "arm,arm920t"
 130                             "arm,arm922t"
 131                             "arm,arm925"
 132                             "arm,arm926e-s"
 133                             "arm,arm926ej-s"
 134                             "arm,arm940t"
 135                             "arm,arm946e-s"
 136                             "arm,arm966e-s"
 137                             "arm,arm968e-s"
 138                             "arm,arm9tdmi"
 139                             "arm,arm1020e"
 140                             "arm,arm1020t"
 141                             "arm,arm1022e"
 142                             "arm,arm1026ej-s"
 143                             "arm,arm1136j-s"
 144                             "arm,arm1136jf-s"
 145                             "arm,arm1156t2-s"
 146                             "arm,arm1156t2f-s"
 147                             "arm,arm1176jzf"
 148                             "arm,arm1176jz-s"
 149                             "arm,arm1176jzf-s"
 150                             "arm,arm11mpcore"
 151                             "arm,cortex-a5"
 152                             "arm,cortex-a7"
 153                             "arm,cortex-a8"
 154                             "arm,cortex-a9"
 155                             "arm,cortex-a12"
 156                             "arm,cortex-a15"
 157                             "arm,cortex-a17"
 158                             "arm,cortex-a53"
 159                             "arm,cortex-a57"
 160                             "arm,cortex-a72"
 161                             "arm,cortex-a73"
 162                             "arm,cortex-m0"
 163                             "arm,cortex-m0+"
 164                             "arm,cortex-m1"
 165                             "arm,cortex-m3"
 166                             "arm,cortex-m4"
 167                             "arm,cortex-r4"
 168                             "arm,cortex-r5"
 169                             "arm,cortex-r7"
 170                             "brcm,brahma-b15"
 171                             "brcm,vulcan"
 172                             "cavium,thunder"
 173                             "faraday,fa526"
 174                             "intel,sa110"
 175                             "intel,sa1100"
 176                             "marvell,feroceon"
 177                             "marvell,mohawk"
 178                             "marvell,pj4a"
 179                             "marvell,pj4b"
 180                             "marvell,sheeva-v5"
 181                             "nvidia,tegra132-denver"
 182                             "nvidia,tegra186-denver"
 183                             "qcom,krait"
 184                             "qcom,kryo"
 185                             "qcom,scorpion"
 186         - enable-method
 187                 Value type: <stringlist>
 188                 Usage and definition depend on ARM architecture version.
 189                         # On ARM v8 64-bit this property is required and must
 190                           be one of:
 191                              "psci"
 192                              "spin-table"
 193                         # On ARM 32-bit systems this property is optional and
 194                           can be one of:
 195                             "allwinner,sun6i-a31"
 196                             "allwinner,sun8i-a23"
 197                             "arm,realview-smp"
 198                             "brcm,bcm11351-cpu-method"
 199                             "brcm,bcm23550"
 200                             "brcm,bcm-nsp-smp"
 201                             "brcm,brahma-b15"
 202                             "marvell,armada-375-smp"
 203                             "marvell,armada-380-smp"
 204                             "marvell,armada-390-smp"
 205                             "marvell,armada-xp-smp"
 206                             "marvell,98dx3236-smp"
 207                             "mediatek,mt6589-smp"
 208                             "mediatek,mt81xx-tz-smp"
 209                             "qcom,gcc-msm8660"
 210                             "qcom,kpss-acc-v1"
 211                             "qcom,kpss-acc-v2"
 212                             "renesas,apmu"
 213                             "rockchip,rk3036-smp"
 214                             "rockchip,rk3066-smp"
 215                             "ste,dbx500-smp"
 216
 217         - cpu-release-addr
 218                 Usage: required for systems that have an "enable-method"
 219                        property value of "spin-table".
 220                 Value type: <prop-encoded-array>
 221                 Definition:
 222                         # On ARM v8 64-bit systems must be a two cell
 223                           property identifying a 64-bit zero-initialised
 224                           memory location.
 225
 226         - qcom,saw
 227                 Usage: required for systems that have an "enable-method"
 228                        property value of "qcom,kpss-acc-v1" or
 229                        "qcom,kpss-acc-v2"
 230                 Value type: <phandle>
 231                 Definition: Specifies the SAW[1] node associated with this CPU.
 232
 233         - qcom,acc
 234                 Usage: required for systems that have an "enable-method"
 235                        property value of "qcom,kpss-acc-v1" or
 236                        "qcom,kpss-acc-v2"
 237                 Value type: <phandle>
 238                 Definition: Specifies the ACC[2] node associated with this CPU.
 239
 240         - cpu-idle-states
 241                 Usage: Optional
 242                 Value type: <prop-encoded-array>
 243                 Definition:
 244                         # List of phandles to idle state nodes supported
 245                           by this cpu [3].
 246
 247         - capacity-dmips-mhz
 248                 Usage: Optional
 249                 Value type: <u32>
 250                 Definition:
 251                         # u32 value representing CPU capacity [3] in
 252                           DMIPS/MHz, relative to highest capacity-dmips-mhz
 253                           in the system.
 254
 255         - rockchip,pmu
 256                 Usage: optional for systems that have an "enable-method"
 257                        property value of "rockchip,rk3066-smp"
 258                        While optional, it is the preferred way to get access to
 259                        the cpu-core power-domains.
 260                 Value type: <phandle>
 261                 Definition: Specifies the syscon node controlling the cpu core
 262                             power domains.
 263
 264         - dynamic-power-coefficient
 265                 Usage: optional
 266                 Value type: <prop-encoded-array>
 267                 Definition: A u32 value that represents the running time dynamic
 268                             power coefficient in units of mW/MHz/uV^2. The
 269                             coefficient can either be calculated from power
 270                             measurements or derived by analysis.
 271
 272                             The dynamic power consumption of the CPU  is
 273                             proportional to the square of the Voltage (V) and
 274                             the clock frequency (f). The coefficient is used to
 275                             calculate the dynamic power as below -
 276
 277                             Pdyn = dynamic-power-coefficient * V^2 * f
 278
 279                             where voltage is in uV, frequency is in MHz.
 280
 281 Example 1 (dual-cluster big.LITTLE system 32-bit):
 282
 283         cpus {
 284                 #size-cells = <0>;
 285                 #address-cells = <1>;
 286
 287                 cpu@0 {
 288                         device_type = "cpu";
 289                         compatible = "arm,cortex-a15";
 290                         reg = <0x0>;
 291                 };
 292
 293                 cpu@1 {
 294                         device_type = "cpu";
 295                         compatible = "arm,cortex-a15";
 296                         reg = <0x1>;
 297                 };
 298
 299                 cpu@100 {
 300                         device_type = "cpu";
 301                         compatible = "arm,cortex-a7";
 302                         reg = <0x100>;
 303                 };
 304
 305                 cpu@101 {
 306                         device_type = "cpu";
 307                         compatible = "arm,cortex-a7";
 308                         reg = <0x101>;
 309                 };
 310         };
 311
 312 Example 2 (Cortex-A8 uniprocessor 32-bit system):
 313
 314         cpus {
 315                 #size-cells = <0>;
 316                 #address-cells = <1>;
 317
 318                 cpu@0 {
 319                         device_type = "cpu";
 320                         compatible = "arm,cortex-a8";
 321                         reg = <0x0>;
 322                 };
 323         };
 324
 325 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 326
 327         cpus {
 328                 #size-cells = <0>;
 329                 #address-cells = <1>;
 330
 331                 cpu@0 {
 332                         device_type = "cpu";
 333                         compatible = "arm,arm926ej-s";
 334                         reg = <0x0>;
 335                 };
 336         };
 337
 338 Example 4 (ARM Cortex-A57 64-bit system):
 339
 340 cpus {
 341         #size-cells = <0>;
 342         #address-cells = <2>;
 343
 344         cpu@0 {
 345                 device_type = "cpu";
 346                 compatible = "arm,cortex-a57";
 347                 reg = <0x0 0x0>;
 348                 enable-method = "spin-table";
 349                 cpu-release-addr = <0 0x20000000>;
 350         };
 351
 352         cpu@1 {
 353                 device_type = "cpu";
 354                 compatible = "arm,cortex-a57";
 355                 reg = <0x0 0x1>;
 356                 enable-method = "spin-table";
 357                 cpu-release-addr = <0 0x20000000>;
 358         };
 359
 360         cpu@100 {
 361                 device_type = "cpu";
 362                 compatible = "arm,cortex-a57";
 363                 reg = <0x0 0x100>;
 364                 enable-method = "spin-table";
 365                 cpu-release-addr = <0 0x20000000>;
 366         };
 367
 368         cpu@101 {
 369                 device_type = "cpu";
 370                 compatible = "arm,cortex-a57";
 371                 reg = <0x0 0x101>;
 372                 enable-method = "spin-table";
 373                 cpu-release-addr = <0 0x20000000>;
 374         };
 375
 376         cpu@10000 {
 377                 device_type = "cpu";
 378                 compatible = "arm,cortex-a57";
 379                 reg = <0x0 0x10000>;
 380                 enable-method = "spin-table";
 381                 cpu-release-addr = <0 0x20000000>;
 382         };
 383
 384         cpu@10001 {
 385                 device_type = "cpu";
 386                 compatible = "arm,cortex-a57";
 387                 reg = <0x0 0x10001>;
 388                 enable-method = "spin-table";
 389                 cpu-release-addr = <0 0x20000000>;
 390         };
 391
 392         cpu@10100 {
 393                 device_type = "cpu";
 394                 compatible = "arm,cortex-a57";
 395                 reg = <0x0 0x10100>;
 396                 enable-method = "spin-table";
 397                 cpu-release-addr = <0 0x20000000>;
 398         };
 399
 400         cpu@10101 {
 401                 device_type = "cpu";
 402                 compatible = "arm,cortex-a57";
 403                 reg = <0x0 0x10101>;
 404                 enable-method = "spin-table";
 405                 cpu-release-addr = <0 0x20000000>;
 406         };
 407
 408         cpu@100000000 {
 409                 device_type = "cpu";
 410                 compatible = "arm,cortex-a57";
 411                 reg = <0x1 0x0>;
 412                 enable-method = "spin-table";
 413                 cpu-release-addr = <0 0x20000000>;
 414         };
 415
 416         cpu@100000001 {
 417                 device_type = "cpu";
 418                 compatible = "arm,cortex-a57";
 419                 reg = <0x1 0x1>;
 420                 enable-method = "spin-table";
 421                 cpu-release-addr = <0 0x20000000>;
 422         };
 423
 424         cpu@100000100 {
 425                 device_type = "cpu";
 426                 compatible = "arm,cortex-a57";
 427                 reg = <0x1 0x100>;
 428                 enable-method = "spin-table";
 429                 cpu-release-addr = <0 0x20000000>;
 430         };
 431
 432         cpu@100000101 {
 433                 device_type = "cpu";
 434                 compatible = "arm,cortex-a57";
 435                 reg = <0x1 0x101>;
 436                 enable-method = "spin-table";
 437                 cpu-release-addr = <0 0x20000000>;
 438         };
 439
 440         cpu@100010000 {
 441                 device_type = "cpu";
 442                 compatible = "arm,cortex-a57";
 443                 reg = <0x1 0x10000>;
 444                 enable-method = "spin-table";
 445                 cpu-release-addr = <0 0x20000000>;
 446         };
 447
 448         cpu@100010001 {
 449                 device_type = "cpu";
 450                 compatible = "arm,cortex-a57";
 451                 reg = <0x1 0x10001>;
 452                 enable-method = "spin-table";
 453                 cpu-release-addr = <0 0x20000000>;
 454         };
 455
 456         cpu@100010100 {
 457                 device_type = "cpu";
 458                 compatible = "arm,cortex-a57";
 459                 reg = <0x1 0x10100>;
 460                 enable-method = "spin-table";
 461                 cpu-release-addr = <0 0x20000000>;
 462         };
 463
 464         cpu@100010101 {
 465                 device_type = "cpu";
 466                 compatible = "arm,cortex-a57";
 467                 reg = <0x1 0x10101>;
 468                 enable-method = "spin-table";
 469                 cpu-release-addr = <0 0x20000000>;
 470         };
 471 };
 472
 473 --
 474 [1] arm/msm/qcom,saw2.txt
 475 [2] arm/msm/qcom,kpss-acc.txt
 476 [3] ARM Linux kernel documentation - idle states bindings
 477     Documentation/devicetree/bindings/arm/idle-states.txt
 478 [3] ARM Linux kernel documentation - cpu capacity bindings
 479     Documentation/devicetree/bindings/arm/cpu-capacity.txt