5 The device tree allows to describe the layout of CPUs in a system through
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
11 https://www.power.org/documentation/epapr-version-1-1/
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
15 ================================
16 Convention used in this document
17 ================================
19 This document follows the conventions described in the ePAPR v1.1, with
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
23 the reg property contained in bits 7 down to 0
25 =====================================
26 cpus and cpu node bindings definition
27 =====================================
29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30 nodes to be present and contain the properties described below.
34 Description: Container of cpu nodes
36 The node name must be "cpus".
38 A cpus node must define the following properties:
44 Definition depends on ARM architecture version and
47 # On uniprocessor ARM architectures previous to v7
48 value must be 1, to enable a simple enumeration
49 scheme for processors that do not have a HW CPU
50 identification register.
51 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
52 value must be 1, that corresponds to CPUID/MPIDR
54 # On ARM v8 64-bit systems value should be set to 2,
55 that corresponds to the MPIDR_EL1 register size.
56 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57 in the system, #address-cells can be set to 1, since
58 MPIDR_EL1[63:32] bits are not used for CPUs
63 Definition: must be set to 0
67 Description: Describes a CPU in an ARM based system
74 Definition: must be "cpu"
76 Usage and definition depend on ARM architecture version and
79 # On uniprocessor ARM architectures previous to v7
80 this property is required and must be set to 0.
82 # On ARM 11 MPcore based systems this property is
83 required and matches the CPUID[11:0] register bits.
85 Bits [11:0] in the reg cell must be set to
86 bits [11:0] in CPU ID register.
88 All other bits in the reg cell must be set to 0.
90 # On 32-bit ARM v7 or later systems this property is
91 required and matches the CPU MPIDR[23:0] register
94 Bits [23:0] in the reg cell must be set to
97 All other bits in the reg cell must be set to 0.
99 # On ARM v8 64-bit systems this property is required
100 and matches the MPIDR_EL1 register affinity bits.
102 * If cpus node's #address-cells property is set to 2
104 The first reg cell bits [7:0] must be set to
105 bits [39:32] of MPIDR_EL1.
107 The second reg cell bits [23:0] must be set to
108 bits [23:0] of MPIDR_EL1.
110 * If cpus node's #address-cells property is set to 1
112 The reg cell bits [23:0] must be set to bits [23:0]
115 All other bits in the reg cells must be set to 0.
120 Definition: should be one of:
181 "nvidia,tegra132-denver"
182 "nvidia,tegra186-denver"
187 Value type: <stringlist>
188 Usage and definition depend on ARM architecture version.
189 # On ARM v8 64-bit this property is required and must
193 # On ARM 32-bit systems this property is optional and
195 "allwinner,sun6i-a31"
196 "allwinner,sun8i-a23"
198 "brcm,bcm11351-cpu-method"
202 "marvell,armada-375-smp"
203 "marvell,armada-380-smp"
204 "marvell,armada-390-smp"
205 "marvell,armada-xp-smp"
206 "marvell,98dx3236-smp"
207 "mediatek,mt6589-smp"
208 "mediatek,mt81xx-tz-smp"
213 "rockchip,rk3036-smp"
214 "rockchip,rk3066-smp"
218 Usage: required for systems that have an "enable-method"
219 property value of "spin-table".
220 Value type: <prop-encoded-array>
222 # On ARM v8 64-bit systems must be a two cell
223 property identifying a 64-bit zero-initialised
227 Usage: required for systems that have an "enable-method"
228 property value of "qcom,kpss-acc-v1" or
230 Value type: <phandle>
231 Definition: Specifies the SAW[1] node associated with this CPU.
234 Usage: required for systems that have an "enable-method"
235 property value of "qcom,kpss-acc-v1" or
237 Value type: <phandle>
238 Definition: Specifies the ACC[2] node associated with this CPU.
242 Value type: <prop-encoded-array>
244 # List of phandles to idle state nodes supported
251 # u32 value representing CPU capacity [3] in
252 DMIPS/MHz, relative to highest capacity-dmips-mhz
256 Usage: optional for systems that have an "enable-method"
257 property value of "rockchip,rk3066-smp"
258 While optional, it is the preferred way to get access to
259 the cpu-core power-domains.
260 Value type: <phandle>
261 Definition: Specifies the syscon node controlling the cpu core
264 - dynamic-power-coefficient
266 Value type: <prop-encoded-array>
267 Definition: A u32 value that represents the running time dynamic
268 power coefficient in units of mW/MHz/uV^2. The
269 coefficient can either be calculated from power
270 measurements or derived by analysis.
272 The dynamic power consumption of the CPU is
273 proportional to the square of the Voltage (V) and
274 the clock frequency (f). The coefficient is used to
275 calculate the dynamic power as below -
277 Pdyn = dynamic-power-coefficient * V^2 * f
279 where voltage is in uV, frequency is in MHz.
281 Example 1 (dual-cluster big.LITTLE system 32-bit):
285 #address-cells = <1>;
289 compatible = "arm,cortex-a15";
295 compatible = "arm,cortex-a15";
301 compatible = "arm,cortex-a7";
307 compatible = "arm,cortex-a7";
312 Example 2 (Cortex-A8 uniprocessor 32-bit system):
316 #address-cells = <1>;
320 compatible = "arm,cortex-a8";
325 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
329 #address-cells = <1>;
333 compatible = "arm,arm926ej-s";
338 Example 4 (ARM Cortex-A57 64-bit system):
342 #address-cells = <2>;
346 compatible = "arm,cortex-a57";
348 enable-method = "spin-table";
349 cpu-release-addr = <0 0x20000000>;
354 compatible = "arm,cortex-a57";
356 enable-method = "spin-table";
357 cpu-release-addr = <0 0x20000000>;
362 compatible = "arm,cortex-a57";
364 enable-method = "spin-table";
365 cpu-release-addr = <0 0x20000000>;
370 compatible = "arm,cortex-a57";
372 enable-method = "spin-table";
373 cpu-release-addr = <0 0x20000000>;
378 compatible = "arm,cortex-a57";
380 enable-method = "spin-table";
381 cpu-release-addr = <0 0x20000000>;
386 compatible = "arm,cortex-a57";
388 enable-method = "spin-table";
389 cpu-release-addr = <0 0x20000000>;
394 compatible = "arm,cortex-a57";
396 enable-method = "spin-table";
397 cpu-release-addr = <0 0x20000000>;
402 compatible = "arm,cortex-a57";
404 enable-method = "spin-table";
405 cpu-release-addr = <0 0x20000000>;
410 compatible = "arm,cortex-a57";
412 enable-method = "spin-table";
413 cpu-release-addr = <0 0x20000000>;
418 compatible = "arm,cortex-a57";
420 enable-method = "spin-table";
421 cpu-release-addr = <0 0x20000000>;
426 compatible = "arm,cortex-a57";
428 enable-method = "spin-table";
429 cpu-release-addr = <0 0x20000000>;
434 compatible = "arm,cortex-a57";
436 enable-method = "spin-table";
437 cpu-release-addr = <0 0x20000000>;
442 compatible = "arm,cortex-a57";
444 enable-method = "spin-table";
445 cpu-release-addr = <0 0x20000000>;
450 compatible = "arm,cortex-a57";
452 enable-method = "spin-table";
453 cpu-release-addr = <0 0x20000000>;
458 compatible = "arm,cortex-a57";
460 enable-method = "spin-table";
461 cpu-release-addr = <0 0x20000000>;
466 compatible = "arm,cortex-a57";
468 enable-method = "spin-table";
469 cpu-release-addr = <0 0x20000000>;
474 [1] arm/msm/qcom,saw2.txt
475 [2] arm/msm/qcom,kpss-acc.txt
476 [3] ARM Linux kernel documentation - idle states bindings
477 Documentation/devicetree/bindings/arm/idle-states.txt
478 [3] ARM Linux kernel documentation - cpu capacity bindings
479 Documentation/devicetree/bindings/arm/cpu-capacity.txt