Documentation/devicetree/bindings/arm/cpus.txt

   1 =================
   2 ARM CPUs bindings
   3 =================
   4
   5 The device tree allows to describe the layout of CPUs in a system through
   6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
   7 defining properties for every cpu.
   8
   9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
  10
  11 https://www.power.org/documentation/epapr-version-1-1/
  12
  13 with updates for 32-bit and 64-bit ARM systems provided in this document.
  14
  15 ================================
  16 Convention used in this document
  17 ================================
  18
  19 This document follows the conventions described in the ePAPR v1.1, with
  20 the addition:
  21
  22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  23   the reg property contained in bits 7 down to 0
  24
  25 =====================================
  26 cpus and cpu node bindings definition
  27 =====================================
  28
  29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
  30 nodes to be present and contain the properties described below.
  31
  32 - cpus node
  33
  34         Description: Container of cpu nodes
  35
  36         The node name must be "cpus".
  37
  38         A cpus node must define the following properties:
  39
  40         - #address-cells
  41                 Usage: required
  42                 Value type: <u32>
  43
  44                 Definition depends on ARM architecture version and
  45                 configuration:
  46
  47                         # On uniprocessor ARM architectures previous to v7
  48                           value must be 1, to enable a simple enumeration
  49                           scheme for processors that do not have a HW CPU
  50                           identification register.
  51                         # On 32-bit ARM 11 MPcore, ARM v7 or later systems
  52                           value must be 1, that corresponds to CPUID/MPIDR
  53                           registers sizes.
  54                         # On ARM v8 64-bit systems value should be set to 2,
  55                           that corresponds to the MPIDR_EL1 register size.
  56                           If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
  57                           in the system, #address-cells can be set to 1, since
  58                           MPIDR_EL1[63:32] bits are not used for CPUs
  59                           identification.
  60         - #size-cells
  61                 Usage: required
  62                 Value type: <u32>
  63                 Definition: must be set to 0
  64
  65 - cpu node
  66
  67         Description: Describes a CPU in an ARM based system
  68
  69         PROPERTIES
  70
  71         - device_type
  72                 Usage: required
  73                 Value type: <string>
  74                 Definition: must be "cpu"
  75         - reg
  76                 Usage and definition depend on ARM architecture version and
  77                 configuration:
  78
  79                         # On uniprocessor ARM architectures previous to v7
  80                           this property is required and must be set to 0.
  81
  82                         # On ARM 11 MPcore based systems this property is
  83                           required and matches the CPUID[11:0] register bits.
  84
  85                           Bits [11:0] in the reg cell must be set to
  86                           bits [11:0] in CPU ID register.
  87
  88                           All other bits in the reg cell must be set to 0.
  89
  90                         # On 32-bit ARM v7 or later systems this property is
  91                           required and matches the CPU MPIDR[23:0] register
  92                           bits.
  93
  94                           Bits [23:0] in the reg cell must be set to
  95                           bits [23:0] in MPIDR.
  96
  97                           All other bits in the reg cell must be set to 0.
  98
  99                         # On ARM v8 64-bit systems this property is required
 100                           and matches the MPIDR_EL1 register affinity bits.
 101
 102                           * If cpus node's #address-cells property is set to 2
 103
 104                             The first reg cell bits [7:0] must be set to
 105                             bits [39:32] of MPIDR_EL1.
 106
 107                             The second reg cell bits [23:0] must be set to
 108                             bits [23:0] of MPIDR_EL1.
 109
 110                           * If cpus node's #address-cells property is set to 1
 111
 112                             The reg cell bits [23:0] must be set to bits [23:0]
 113                             of MPIDR_EL1.
 114
 115                           All other bits in the reg cells must be set to 0.
 116
 117         - compatible:
 118                 Usage: required
 119                 Value type: <string>
 120                 Definition: should be one of:
 121                             "arm,arm710t"
 122                             "arm,arm720t"
 123                             "arm,arm740t"
 124                             "arm,arm7ej-s"
 125                             "arm,arm7tdmi"
 126                             "arm,arm7tdmi-s"
 127                             "arm,arm9es"
 128                             "arm,arm9ej-s"
 129                             "arm,arm920t"
 130                             "arm,arm922t"
 131                             "arm,arm925"
 132                             "arm,arm926e-s"
 133                             "arm,arm926ej-s"
 134                             "arm,arm940t"
 135                             "arm,arm946e-s"
 136                             "arm,arm966e-s"
 137                             "arm,arm968e-s"
 138                             "arm,arm9tdmi"
 139                             "arm,arm1020e"
 140                             "arm,arm1020t"
 141                             "arm,arm1022e"
 142                             "arm,arm1026ej-s"
 143                             "arm,arm1136j-s"
 144                             "arm,arm1136jf-s"
 145                             "arm,arm1156t2-s"
 146                             "arm,arm1156t2f-s"
 147                             "arm,arm1176jzf"
 148                             "arm,arm1176jz-s"
 149                             "arm,arm1176jzf-s"
 150                             "arm,arm11mpcore"
 151                             "arm,cortex-a5"
 152                             "arm,cortex-a7"
 153                             "arm,cortex-a8"
 154                             "arm,cortex-a9"
 155                             "arm,cortex-a15"
 156                             "arm,cortex-a53"
 157                             "arm,cortex-a57"
 158                             "arm,cortex-m0"
 159                             "arm,cortex-m0+"
 160                             "arm,cortex-m1"
 161                             "arm,cortex-m3"
 162                             "arm,cortex-m4"
 163                             "arm,cortex-r4"
 164                             "arm,cortex-r5"
 165                             "arm,cortex-r7"
 166                             "faraday,fa526"
 167                             "intel,sa110"
 168                             "intel,sa1100"
 169                             "marvell,feroceon"
 170                             "marvell,mohawk"
 171                             "marvell,pj4a"
 172                             "marvell,pj4b"
 173                             "marvell,sheeva-v5"
 174                             "qcom,krait"
 175                             "qcom,scorpion"
 176         - enable-method
 177                 Value type: <stringlist>
 178                 Usage and definition depend on ARM architecture version.
 179                         # On ARM v8 64-bit this property is required and must
 180                           be one of:
 181                              "spin-table"
 182                              "psci"
 183                         # On ARM 32-bit systems this property is optional and
 184                           can be one of:
 185                             "qcom,gcc-msm8660"
 186                             "qcom,kpss-acc-v1"
 187                             "qcom,kpss-acc-v2"
 188
 189         - cpu-release-addr
 190                 Usage: required for systems that have an "enable-method"
 191                        property value of "spin-table".
 192                 Value type: <prop-encoded-array>
 193                 Definition:
 194                         # On ARM v8 64-bit systems must be a two cell
 195                           property identifying a 64-bit zero-initialised
 196                           memory location.
 197
 198         - qcom,saw
 199                 Usage: required for systems that have an "enable-method"
 200                        property value of "qcom,kpss-acc-v1" or
 201                        "qcom,kpss-acc-v2"
 202                 Value type: <phandle>
 203                 Definition: Specifies the SAW[1] node associated with this CPU.
 204
 205         - qcom,acc
 206                 Usage: required for systems that have an "enable-method"
 207                        property value of "qcom,kpss-acc-v1" or
 208                        "qcom,kpss-acc-v2"
 209                 Value type: <phandle>
 210                 Definition: Specifies the ACC[2] node associated with this CPU.
 211
 212
 213 Example 1 (dual-cluster big.LITTLE system 32-bit):
 214
 215         cpus {
 216                 #size-cells = <0>;
 217                 #address-cells = <1>;
 218
 219                 cpu@0 {
 220                         device_type = "cpu";
 221                         compatible = "arm,cortex-a15";
 222                         reg = <0x0>;
 223                 };
 224
 225                 cpu@1 {
 226                         device_type = "cpu";
 227                         compatible = "arm,cortex-a15";
 228                         reg = <0x1>;
 229                 };
 230
 231                 cpu@100 {
 232                         device_type = "cpu";
 233                         compatible = "arm,cortex-a7";
 234                         reg = <0x100>;
 235                 };
 236
 237                 cpu@101 {
 238                         device_type = "cpu";
 239                         compatible = "arm,cortex-a7";
 240                         reg = <0x101>;
 241                 };
 242         };
 243
 244 Example 2 (Cortex-A8 uniprocessor 32-bit system):
 245
 246         cpus {
 247                 #size-cells = <0>;
 248                 #address-cells = <1>;
 249
 250                 cpu@0 {
 251                         device_type = "cpu";
 252                         compatible = "arm,cortex-a8";
 253                         reg = <0x0>;
 254                 };
 255         };
 256
 257 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 258
 259         cpus {
 260                 #size-cells = <0>;
 261                 #address-cells = <1>;
 262
 263                 cpu@0 {
 264                         device_type = "cpu";
 265                         compatible = "arm,arm926ej-s";
 266                         reg = <0x0>;
 267                 };
 268         };
 269
 270 Example 4 (ARM Cortex-A57 64-bit system):
 271
 272 cpus {
 273         #size-cells = <0>;
 274         #address-cells = <2>;
 275
 276         cpu@0 {
 277                 device_type = "cpu";
 278                 compatible = "arm,cortex-a57";
 279                 reg = <0x0 0x0>;
 280                 enable-method = "spin-table";
 281                 cpu-release-addr = <0 0x20000000>;
 282         };
 283
 284         cpu@1 {
 285                 device_type = "cpu";
 286                 compatible = "arm,cortex-a57";
 287                 reg = <0x0 0x1>;
 288                 enable-method = "spin-table";
 289                 cpu-release-addr = <0 0x20000000>;
 290         };
 291
 292         cpu@100 {
 293                 device_type = "cpu";
 294                 compatible = "arm,cortex-a57";
 295                 reg = <0x0 0x100>;
 296                 enable-method = "spin-table";
 297                 cpu-release-addr = <0 0x20000000>;
 298         };
 299
 300         cpu@101 {
 301                 device_type = "cpu";
 302                 compatible = "arm,cortex-a57";
 303                 reg = <0x0 0x101>;
 304                 enable-method = "spin-table";
 305                 cpu-release-addr = <0 0x20000000>;
 306         };
 307
 308         cpu@10000 {
 309                 device_type = "cpu";
 310                 compatible = "arm,cortex-a57";
 311                 reg = <0x0 0x10000>;
 312                 enable-method = "spin-table";
 313                 cpu-release-addr = <0 0x20000000>;
 314         };
 315
 316         cpu@10001 {
 317                 device_type = "cpu";
 318                 compatible = "arm,cortex-a57";
 319                 reg = <0x0 0x10001>;
 320                 enable-method = "spin-table";
 321                 cpu-release-addr = <0 0x20000000>;
 322         };
 323
 324         cpu@10100 {
 325                 device_type = "cpu";
 326                 compatible = "arm,cortex-a57";
 327                 reg = <0x0 0x10100>;
 328                 enable-method = "spin-table";
 329                 cpu-release-addr = <0 0x20000000>;
 330         };
 331
 332         cpu@10101 {
 333                 device_type = "cpu";
 334                 compatible = "arm,cortex-a57";
 335                 reg = <0x0 0x10101>;
 336                 enable-method = "spin-table";
 337                 cpu-release-addr = <0 0x20000000>;
 338         };
 339
 340         cpu@100000000 {
 341                 device_type = "cpu";
 342                 compatible = "arm,cortex-a57";
 343                 reg = <0x1 0x0>;
 344                 enable-method = "spin-table";
 345                 cpu-release-addr = <0 0x20000000>;
 346         };
 347
 348         cpu@100000001 {
 349                 device_type = "cpu";
 350                 compatible = "arm,cortex-a57";
 351                 reg = <0x1 0x1>;
 352                 enable-method = "spin-table";
 353                 cpu-release-addr = <0 0x20000000>;
 354         };
 355
 356         cpu@100000100 {
 357                 device_type = "cpu";
 358                 compatible = "arm,cortex-a57";
 359                 reg = <0x1 0x100>;
 360                 enable-method = "spin-table";
 361                 cpu-release-addr = <0 0x20000000>;
 362         };
 363
 364         cpu@100000101 {
 365                 device_type = "cpu";
 366                 compatible = "arm,cortex-a57";
 367                 reg = <0x1 0x101>;
 368                 enable-method = "spin-table";
 369                 cpu-release-addr = <0 0x20000000>;
 370         };
 371
 372         cpu@100010000 {
 373                 device_type = "cpu";
 374                 compatible = "arm,cortex-a57";
 375                 reg = <0x1 0x10000>;
 376                 enable-method = "spin-table";
 377                 cpu-release-addr = <0 0x20000000>;
 378         };
 379
 380         cpu@100010001 {
 381                 device_type = "cpu";
 382                 compatible = "arm,cortex-a57";
 383                 reg = <0x1 0x10001>;
 384                 enable-method = "spin-table";
 385                 cpu-release-addr = <0 0x20000000>;
 386         };
 387
 388         cpu@100010100 {
 389                 device_type = "cpu";
 390                 compatible = "arm,cortex-a57";
 391                 reg = <0x1 0x10100>;
 392                 enable-method = "spin-table";
 393                 cpu-release-addr = <0 0x20000000>;
 394         };
 395
 396         cpu@100010101 {
 397                 device_type = "cpu";
 398                 compatible = "arm,cortex-a57";
 399                 reg = <0x1 0x10101>;
 400                 enable-method = "spin-table";
 401                 cpu-release-addr = <0 0x20000000>;
 402         };
 403 };
 404
 405 --
 406 [1] arm/msm/qcom,saw2.txt
 407 [2] arm/msm/qcom,kpss-acc.txt