Documentation/devicetree/bindings/arm/cpus.txt

   1 =================
   2 ARM CPUs bindings
   3 =================
   4
   5 The device tree allows to describe the layout of CPUs in a system through
   6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
   7 defining properties for every cpu.
   8
   9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
  10
  11 https://www.power.org/documentation/epapr-version-1-1/
  12
  13 with updates for 32-bit and 64-bit ARM systems provided in this document.
  14
  15 ================================
  16 Convention used in this document
  17 ================================
  18
  19 This document follows the conventions described in the ePAPR v1.1, with
  20 the addition:
  21
  22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  23   the reg property contained in bits 7 down to 0
  24
  25 =====================================
  26 cpus and cpu node bindings definition
  27 =====================================
  28
  29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
  30 nodes to be present and contain the properties described below.
  31
  32 - cpus node
  33
  34         Description: Container of cpu nodes
  35
  36         The node name must be "cpus".
  37
  38         A cpus node must define the following properties:
  39
  40         - #address-cells
  41                 Usage: required
  42                 Value type: <u32>
  43
  44                 Definition depends on ARM architecture version and
  45                 configuration:
  46
  47                         # On uniprocessor ARM architectures previous to v7
  48                           value must be 1, to enable a simple enumeration
  49                           scheme for processors that do not have a HW CPU
  50                           identification register.
  51                         # On 32-bit ARM 11 MPcore, ARM v7 or later systems
  52                           value must be 1, that corresponds to CPUID/MPIDR
  53                           registers sizes.
  54                         # On ARM v8 64-bit systems value should be set to 2,
  55                           that corresponds to the MPIDR_EL1 register size.
  56                           If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
  57                           in the system, #address-cells can be set to 1, since
  58                           MPIDR_EL1[63:32] bits are not used for CPUs
  59                           identification.
  60         - #size-cells
  61                 Usage: required
  62                 Value type: <u32>
  63                 Definition: must be set to 0
  64
  65 - cpu node
  66
  67         Description: Describes a CPU in an ARM based system
  68
  69         PROPERTIES
  70
  71         - device_type
  72                 Usage: required
  73                 Value type: <string>
  74                 Definition: must be "cpu"
  75         - reg
  76                 Usage and definition depend on ARM architecture version and
  77                 configuration:
  78
  79                         # On uniprocessor ARM architectures previous to v7
  80                           this property is required and must be set to 0.
  81
  82                         # On ARM 11 MPcore based systems this property is
  83                           required and matches the CPUID[11:0] register bits.
  84
  85                           Bits [11:0] in the reg cell must be set to
  86                           bits [11:0] in CPU ID register.
  87
  88                           All other bits in the reg cell must be set to 0.
  89
  90                         # On 32-bit ARM v7 or later systems this property is
  91                           required and matches the CPU MPIDR[23:0] register
  92                           bits.
  93
  94                           Bits [23:0] in the reg cell must be set to
  95                           bits [23:0] in MPIDR.
  96
  97                           All other bits in the reg cell must be set to 0.
  98
  99                         # On ARM v8 64-bit systems this property is required
 100                           and matches the MPIDR_EL1 register affinity bits.
 101
 102                           * If cpus node's #address-cells property is set to 2
 103
 104                             The first reg cell bits [7:0] must be set to
 105                             bits [39:32] of MPIDR_EL1.
 106
 107                             The second reg cell bits [23:0] must be set to
 108                             bits [23:0] of MPIDR_EL1.
 109
 110                           * If cpus node's #address-cells property is set to 1
 111
 112                             The reg cell bits [23:0] must be set to bits [23:0]
 113                             of MPIDR_EL1.
 114
 115                           All other bits in the reg cells must be set to 0.
 116
 117         - compatible:
 118                 Usage: required
 119                 Value type: <string>
 120                 Definition: should be one of:
 121                             "arm,arm710t"
 122                             "arm,arm720t"
 123                             "arm,arm740t"
 124                             "arm,arm7ej-s"
 125                             "arm,arm7tdmi"
 126                             "arm,arm7tdmi-s"
 127                             "arm,arm9es"
 128                             "arm,arm9ej-s"
 129                             "arm,arm920t"
 130                             "arm,arm922t"
 131                             "arm,arm925"
 132                             "arm,arm926e-s"
 133                             "arm,arm926ej-s"
 134                             "arm,arm940t"
 135                             "arm,arm946e-s"
 136                             "arm,arm966e-s"
 137                             "arm,arm968e-s"
 138                             "arm,arm9tdmi"
 139                             "arm,arm1020e"
 140                             "arm,arm1020t"
 141                             "arm,arm1022e"
 142                             "arm,arm1026ej-s"
 143                             "arm,arm1136j-s"
 144                             "arm,arm1136jf-s"
 145                             "arm,arm1156t2-s"
 146                             "arm,arm1156t2f-s"
 147                             "arm,arm1176jzf"
 148                             "arm,arm1176jz-s"
 149                             "arm,arm1176jzf-s"
 150                             "arm,arm11mpcore"
 151                             "arm,cortex-a5"
 152                             "arm,cortex-a7"
 153                             "arm,cortex-a8"
 154                             "arm,cortex-a9"
 155                             "arm,cortex-a12"
 156                             "arm,cortex-a15"
 157                             "arm,cortex-a17"
 158                             "arm,cortex-a53"
 159                             "arm,cortex-a57"
 160                             "arm,cortex-a72"
 161                             "arm,cortex-a73"
 162                             "arm,cortex-m0"
 163                             "arm,cortex-m0+"
 164                             "arm,cortex-m1"
 165                             "arm,cortex-m3"
 166                             "arm,cortex-m4"
 167                             "arm,cortex-r4"
 168                             "arm,cortex-r5"
 169                             "arm,cortex-r7"
 170                             "brcm,brahma-b15"
 171                             "brcm,vulcan"
 172                             "cavium,thunder"
 173                             "cavium,thunder2"
 174                             "faraday,fa526"
 175                             "intel,sa110"
 176                             "intel,sa1100"
 177                             "marvell,feroceon"
 178                             "marvell,mohawk"
 179                             "marvell,pj4a"
 180                             "marvell,pj4b"
 181                             "marvell,sheeva-v5"
 182                             "nvidia,tegra132-denver"
 183                             "nvidia,tegra186-denver"
 184                             "qcom,krait"
 185                             "qcom,kryo"
 186                             "qcom,scorpion"
 187         - enable-method
 188                 Value type: <stringlist>
 189                 Usage and definition depend on ARM architecture version.
 190                         # On ARM v8 64-bit this property is required and must
 191                           be one of:
 192                              "psci"
 193                              "spin-table"
 194                         # On ARM 32-bit systems this property is optional and
 195                           can be one of:
 196                             "allwinner,sun6i-a31"
 197                             "allwinner,sun8i-a23"
 198                             "arm,realview-smp"
 199                             "brcm,bcm11351-cpu-method"
 200                             "brcm,bcm23550"
 201                             "brcm,bcm-nsp-smp"
 202                             "brcm,brahma-b15"
 203                             "marvell,armada-375-smp"
 204                             "marvell,armada-380-smp"
 205                             "marvell,armada-390-smp"
 206                             "marvell,armada-xp-smp"
 207                             "marvell,98dx3236-smp"
 208                             "mediatek,mt6589-smp"
 209                             "mediatek,mt81xx-tz-smp"
 210                             "qcom,gcc-msm8660"
 211                             "qcom,kpss-acc-v1"
 212                             "qcom,kpss-acc-v2"
 213                             "renesas,apmu"
 214                             "rockchip,rk3036-smp"
 215                             "rockchip,rk3066-smp"
 216                             "ste,dbx500-smp"
 217
 218         - cpu-release-addr
 219                 Usage: required for systems that have an "enable-method"
 220                        property value of "spin-table".
 221                 Value type: <prop-encoded-array>
 222                 Definition:
 223                         # On ARM v8 64-bit systems must be a two cell
 224                           property identifying a 64-bit zero-initialised
 225                           memory location.
 226
 227         - qcom,saw
 228                 Usage: required for systems that have an "enable-method"
 229                        property value of "qcom,kpss-acc-v1" or
 230                        "qcom,kpss-acc-v2"
 231                 Value type: <phandle>
 232                 Definition: Specifies the SAW[1] node associated with this CPU.
 233
 234         - qcom,acc
 235                 Usage: required for systems that have an "enable-method"
 236                        property value of "qcom,kpss-acc-v1" or
 237                        "qcom,kpss-acc-v2"
 238                 Value type: <phandle>
 239                 Definition: Specifies the ACC[2] node associated with this CPU.
 240
 241         - cpu-idle-states
 242                 Usage: Optional
 243                 Value type: <prop-encoded-array>
 244                 Definition:
 245                         # List of phandles to idle state nodes supported
 246                           by this cpu [3].
 247
 248         - capacity-dmips-mhz
 249                 Usage: Optional
 250                 Value type: <u32>
 251                 Definition:
 252                         # u32 value representing CPU capacity [3] in
 253                           DMIPS/MHz, relative to highest capacity-dmips-mhz
 254                           in the system.
 255
 256         - rockchip,pmu
 257                 Usage: optional for systems that have an "enable-method"
 258                        property value of "rockchip,rk3066-smp"
 259                        While optional, it is the preferred way to get access to
 260                        the cpu-core power-domains.
 261                 Value type: <phandle>
 262                 Definition: Specifies the syscon node controlling the cpu core
 263                             power domains.
 264
 265         - dynamic-power-coefficient
 266                 Usage: optional
 267                 Value type: <prop-encoded-array>
 268                 Definition: A u32 value that represents the running time dynamic
 269                             power coefficient in units of mW/MHz/uV^2. The
 270                             coefficient can either be calculated from power
 271                             measurements or derived by analysis.
 272
 273                             The dynamic power consumption of the CPU  is
 274                             proportional to the square of the Voltage (V) and
 275                             the clock frequency (f). The coefficient is used to
 276                             calculate the dynamic power as below -
 277
 278                             Pdyn = dynamic-power-coefficient * V^2 * f
 279
 280                             where voltage is in uV, frequency is in MHz.
 281
 282 Example 1 (dual-cluster big.LITTLE system 32-bit):
 283
 284         cpus {
 285                 #size-cells = <0>;
 286                 #address-cells = <1>;
 287
 288                 cpu@0 {
 289                         device_type = "cpu";
 290                         compatible = "arm,cortex-a15";
 291                         reg = <0x0>;
 292                 };
 293
 294                 cpu@1 {
 295                         device_type = "cpu";
 296                         compatible = "arm,cortex-a15";
 297                         reg = <0x1>;
 298                 };
 299
 300                 cpu@100 {
 301                         device_type = "cpu";
 302                         compatible = "arm,cortex-a7";
 303                         reg = <0x100>;
 304                 };
 305
 306                 cpu@101 {
 307                         device_type = "cpu";
 308                         compatible = "arm,cortex-a7";
 309                         reg = <0x101>;
 310                 };
 311         };
 312
 313 Example 2 (Cortex-A8 uniprocessor 32-bit system):
 314
 315         cpus {
 316                 #size-cells = <0>;
 317                 #address-cells = <1>;
 318
 319                 cpu@0 {
 320                         device_type = "cpu";
 321                         compatible = "arm,cortex-a8";
 322                         reg = <0x0>;
 323                 };
 324         };
 325
 326 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 327
 328         cpus {
 329                 #size-cells = <0>;
 330                 #address-cells = <1>;
 331
 332                 cpu@0 {
 333                         device_type = "cpu";
 334                         compatible = "arm,arm926ej-s";
 335                         reg = <0x0>;
 336                 };
 337         };
 338
 339 Example 4 (ARM Cortex-A57 64-bit system):
 340
 341 cpus {
 342         #size-cells = <0>;
 343         #address-cells = <2>;
 344
 345         cpu@0 {
 346                 device_type = "cpu";
 347                 compatible = "arm,cortex-a57";
 348                 reg = <0x0 0x0>;
 349                 enable-method = "spin-table";
 350                 cpu-release-addr = <0 0x20000000>;
 351         };
 352
 353         cpu@1 {
 354                 device_type = "cpu";
 355                 compatible = "arm,cortex-a57";
 356                 reg = <0x0 0x1>;
 357                 enable-method = "spin-table";
 358                 cpu-release-addr = <0 0x20000000>;
 359         };
 360
 361         cpu@100 {
 362                 device_type = "cpu";
 363                 compatible = "arm,cortex-a57";
 364                 reg = <0x0 0x100>;
 365                 enable-method = "spin-table";
 366                 cpu-release-addr = <0 0x20000000>;
 367         };
 368
 369         cpu@101 {
 370                 device_type = "cpu";
 371                 compatible = "arm,cortex-a57";
 372                 reg = <0x0 0x101>;
 373                 enable-method = "spin-table";
 374                 cpu-release-addr = <0 0x20000000>;
 375         };
 376
 377         cpu@10000 {
 378                 device_type = "cpu";
 379                 compatible = "arm,cortex-a57";
 380                 reg = <0x0 0x10000>;
 381                 enable-method = "spin-table";
 382                 cpu-release-addr = <0 0x20000000>;
 383         };
 384
 385         cpu@10001 {
 386                 device_type = "cpu";
 387                 compatible = "arm,cortex-a57";
 388                 reg = <0x0 0x10001>;
 389                 enable-method = "spin-table";
 390                 cpu-release-addr = <0 0x20000000>;
 391         };
 392
 393         cpu@10100 {
 394                 device_type = "cpu";
 395                 compatible = "arm,cortex-a57";
 396                 reg = <0x0 0x10100>;
 397                 enable-method = "spin-table";
 398                 cpu-release-addr = <0 0x20000000>;
 399         };
 400
 401         cpu@10101 {
 402                 device_type = "cpu";
 403                 compatible = "arm,cortex-a57";
 404                 reg = <0x0 0x10101>;
 405                 enable-method = "spin-table";
 406                 cpu-release-addr = <0 0x20000000>;
 407         };
 408
 409         cpu@100000000 {
 410                 device_type = "cpu";
 411                 compatible = "arm,cortex-a57";
 412                 reg = <0x1 0x0>;
 413                 enable-method = "spin-table";
 414                 cpu-release-addr = <0 0x20000000>;
 415         };
 416
 417         cpu@100000001 {
 418                 device_type = "cpu";
 419                 compatible = "arm,cortex-a57";
 420                 reg = <0x1 0x1>;
 421                 enable-method = "spin-table";
 422                 cpu-release-addr = <0 0x20000000>;
 423         };
 424
 425         cpu@100000100 {
 426                 device_type = "cpu";
 427                 compatible = "arm,cortex-a57";
 428                 reg = <0x1 0x100>;
 429                 enable-method = "spin-table";
 430                 cpu-release-addr = <0 0x20000000>;
 431         };
 432
 433         cpu@100000101 {
 434                 device_type = "cpu";
 435                 compatible = "arm,cortex-a57";
 436                 reg = <0x1 0x101>;
 437                 enable-method = "spin-table";
 438                 cpu-release-addr = <0 0x20000000>;
 439         };
 440
 441         cpu@100010000 {
 442                 device_type = "cpu";
 443                 compatible = "arm,cortex-a57";
 444                 reg = <0x1 0x10000>;
 445                 enable-method = "spin-table";
 446                 cpu-release-addr = <0 0x20000000>;
 447         };
 448
 449         cpu@100010001 {
 450                 device_type = "cpu";
 451                 compatible = "arm,cortex-a57";
 452                 reg = <0x1 0x10001>;
 453                 enable-method = "spin-table";
 454                 cpu-release-addr = <0 0x20000000>;
 455         };
 456
 457         cpu@100010100 {
 458                 device_type = "cpu";
 459                 compatible = "arm,cortex-a57";
 460                 reg = <0x1 0x10100>;
 461                 enable-method = "spin-table";
 462                 cpu-release-addr = <0 0x20000000>;
 463         };
 464
 465         cpu@100010101 {
 466                 device_type = "cpu";
 467                 compatible = "arm,cortex-a57";
 468                 reg = <0x1 0x10101>;
 469                 enable-method = "spin-table";
 470                 cpu-release-addr = <0 0x20000000>;
 471         };
 472 };
 473
 474 --
 475 [1] arm/msm/qcom,saw2.txt
 476 [2] arm/msm/qcom,kpss-acc.txt
 477 [3] ARM Linux kernel documentation - idle states bindings
 478     Documentation/devicetree/bindings/arm/idle-states.txt
 479 [3] ARM Linux kernel documentation - cpu capacity bindings
 480     Documentation/devicetree/bindings/arm/cpu-capacity.txt