1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
4 specification and can be connected in various topologies to suit a particular
5 SoCs tracing needs. These trace components can generally be classified as
6 sinks, links and sources. Trace data produced by one or more sources flows
7 through the intermediate links connecting the source to the currently selected
8 sink. Each CoreSight component device should use these properties to describe
9 its hardware characteristcs.
11 * Required properties for all components *except* non-configurable replicators:
13 * compatible: These have to be supplemented with "arm,primecell" as
14 drivers are using the AMBA bus interface. Possible values include:
15 - Embedded Trace Buffer (version 1.0):
16 "arm,coresight-etb10", "arm,primecell";
18 - Trace Port Interface Unit:
19 "arm,coresight-tpiu", "arm,primecell";
21 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
22 Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
23 configuration. The configuration mode (ETB, ETF, ETR) is
24 discovered at boot time when the device is probed.
25 "arm,coresight-tmc", "arm,primecell";
28 "arm,coresight-funnel", "arm,primecell";
30 - Embedded Trace Macrocell (version 3.x) and
31 Program Flow Trace Macrocell:
32 "arm,coresight-etm3x", "arm,primecell";
34 - Embedded Trace Macrocell (version 4.x):
35 "arm,coresight-etm4x", "arm,primecell";
37 - Coresight programmable Replicator :
38 "arm,coresight-dynamic-replicator", "arm,primecell";
40 - System Trace Macrocell:
41 "arm,coresight-stm", "arm,primecell"; [1]
42 - Coresight Address Translation Unit (CATU)
43 "arm,coresight-catu", "arm,primecell";
45 * reg: physical base address and length of the register
46 set(s) of the component.
48 * clocks: the clocks associated to this component.
50 * clock-names: the name of the clocks referenced by the code.
51 Since we are using the AMBA framework, the name of the clock
52 providing the interconnect should be "apb_pclk", and some
53 coresight blocks also have an additional clock "atclk", which
54 clocks the core of that coresight component. The latter clock
57 * port or ports: see "Graph bindings for Coresight" below.
59 * Additional required properties for System Trace Macrocells (STM):
60 * reg: along with the physical base address and length of the register
61 set as described above, another entry is required to describe the
62 mapping of the extended stimulus port area.
64 * reg-names: the only acceptable values are "stm-base" and
65 "stm-stimulus-base", each corresponding to the areas defined in "reg".
67 * Required properties for devices that don't show up on the AMBA bus, such as
68 non-configurable replicators:
70 * compatible: Currently supported value is (note the absence of the
72 - "arm,coresight-replicator"
74 * port or ports: see "Graph bindings for Coresight" below.
76 * Optional properties for ETM/PTMs:
78 * arm,cp14: must be present if the system accesses ETM/PTM management
79 registers via co-processor 14.
81 * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
82 source is considered to belong to CPU0.
84 * Optional property for TMC:
86 * arm,buffer-size: size of contiguous buffer space for TMC ETR
87 (embedded trace router). This property is obsolete. The buffer size
88 can be configured dynamically via buffer_size property in sysfs.
90 * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
91 use the SG mode on this system.
93 * Optional property for CATU :
94 * interrupts : Exactly one SPI may be listed for reporting the address
97 Graph bindings for Coresight
98 -------------------------------
100 Coresight components are interconnected to create a data path for the flow of
101 trace data generated from the "sources" to their collection points "sink".
102 Each coresight component must describe the "input" and "output" connections.
103 The connections must be described via generic DT graph bindings as described
104 by the "bindings/graph.txt", where each "port" along with an "endpoint"
105 component represents a hardware port and the connection.
107 * All output ports must be listed inside a child node named "out-ports"
108 * All input ports must be listed inside a child node named "in-ports".
109 * Port address must match the hardware port number.
115 compatible = "arm,coresight-etb10", "arm,primecell";
116 reg = <0 0x20010000 0 0x1000>;
118 clocks = <&oscclk6a>;
119 clock-names = "apb_pclk";
122 etb_in_port: endpoint@0 {
123 remote-endpoint = <&replicator_out_port0>;
130 compatible = "arm,coresight-tpiu", "arm,primecell";
131 reg = <0 0x20030000 0 0x1000>;
133 clocks = <&oscclk6a>;
134 clock-names = "apb_pclk";
137 tpiu_in_port: endpoint@0 {
138 remote-endpoint = <&replicator_out_port1>;
145 compatible = "arm,coresight-tmc", "arm,primecell";
146 reg = <0 0x20070000 0 0x1000>;
148 clocks = <&oscclk6a>;
149 clock-names = "apb_pclk";
152 etr_in_port: endpoint {
153 remote-endpoint = <&replicator2_out_port0>;
160 etr_out_port: endpoint {
161 remote-endpoint = <&catu_in_port>;
169 /* non-configurable replicators don't show up on the
170 * AMBA bus. As such no need to add "arm,primecell".
172 compatible = "arm,coresight-replicator";
175 #address-cells = <1>;
178 /* replicator output ports */
181 replicator_out_port0: endpoint {
182 remote-endpoint = <&etb_in_port>;
188 replicator_out_port1: endpoint {
189 remote-endpoint = <&tpiu_in_port>;
196 replicator_in_port0: endpoint {
197 remote-endpoint = <&funnel_out_port0>;
204 compatible = "arm,coresight-funnel", "arm,primecell";
205 reg = <0 0x20040000 0 0x1000>;
207 clocks = <&oscclk6a>;
208 clock-names = "apb_pclk";
211 funnel_out_port0: endpoint {
213 <&replicator_in_port0>;
219 #address-cells = <1>;
224 funnel_in_port0: endpoint {
225 remote-endpoint = <&ptm0_out_port>;
231 funnel_in_port1: endpoint {
232 remote-endpoint = <&ptm1_out_port>;
238 funnel_in_port2: endpoint {
239 remote-endpoint = <&etm0_out_port>;
248 compatible = "arm,coresight-etm3x", "arm,primecell";
249 reg = <0 0x2201c000 0 0x1000>;
252 clocks = <&oscclk6a>;
253 clock-names = "apb_pclk";
256 ptm0_out_port: endpoint {
257 remote-endpoint = <&funnel_in_port0>;
264 compatible = "arm,coresight-etm3x", "arm,primecell";
265 reg = <0 0x2201d000 0 0x1000>;
268 clocks = <&oscclk6a>;
269 clock-names = "apb_pclk";
272 ptm1_out_port: endpoint {
273 remote-endpoint = <&funnel_in_port1>;
281 compatible = "arm,coresight-stm", "arm,primecell";
282 reg = <0 0x20100000 0 0x1000>,
283 <0 0x28000000 0 0x180000>;
284 reg-names = "stm-base", "stm-stimulus-base";
286 clocks = <&soc_smc50mhz>;
287 clock-names = "apb_pclk";
290 stm_out_port: endpoint {
291 remote-endpoint = <&main_funnel_in_port2>;
300 compatible = "arm,coresight-catu", "arm,primecell";
301 reg = <0 0x207e0000 0 0x1000>;
303 clocks = <&oscclk6a>;
304 clock-names = "apb_pclk";
306 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
309 catu_in_port: endpoint {
310 remote-endpoint = <&etr_out_port>;
316 [1]. There is currently two version of STM: STM32 and STM500. Both
317 have the same HW interface and as such don't need an explicit binding name.