Documentation/devicetree/bindings/arm/coresight.txt

   1 * CoreSight Components:
   2
   3 CoreSight components are compliant with the ARM CoreSight architecture
   4 specification and can be connected in various topologies to suit a particular
   5 SoCs tracing needs. These trace components can generally be classified as
   6 sinks, links and sources. Trace data produced by one or more sources flows
   7 through the intermediate links connecting the source to the currently selected
   8 sink. Each CoreSight component device should use these properties to describe
   9 its hardware characteristcs.
  10
  11 * Required properties for all components *except* non-configurable replicators:
  12
  13         * compatible: These have to be supplemented with "arm,primecell" as
  14           drivers are using the AMBA bus interface.  Possible values include:
  15                 - Embedded Trace Buffer (version 1.0):
  16                         "arm,coresight-etb10", "arm,primecell";
  17
  18                 - Trace Port Interface Unit:
  19                         "arm,coresight-tpiu", "arm,primecell";
  20
  21                 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
  22                   Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
  23                   configuration.  The configuration mode (ETB, ETF, ETR) is
  24                   discovered at boot time when the device is probed.
  25                         "arm,coresight-tmc", "arm,primecell";
  26
  27                 - Trace Funnel:
  28                         "arm,coresight-funnel", "arm,primecell";
  29
  30                 - Embedded Trace Macrocell (version 3.x) and
  31                                         Program Flow Trace Macrocell:
  32                         "arm,coresight-etm3x", "arm,primecell";
  33
  34                 - Embedded Trace Macrocell (version 4.x):
  35                         "arm,coresight-etm4x", "arm,primecell";
  36
  37                 - Coresight programmable Replicator :
  38                         "arm,coresight-dynamic-replicator", "arm,primecell";
  39
  40                 - System Trace Macrocell:
  41                         "arm,coresight-stm", "arm,primecell"; [1]
  42                 - Coresight Address Translation Unit (CATU)
  43                         "arm,coresight-catu", "arm,primecell";
  44
  45         * reg: physical base address and length of the register
  46           set(s) of the component.
  47
  48         * clocks: the clocks associated to this component.
  49
  50         * clock-names: the name of the clocks referenced by the code.
  51           Since we are using the AMBA framework, the name of the clock
  52           providing the interconnect should be "apb_pclk", and some
  53           coresight blocks also have an additional clock "atclk", which
  54           clocks the core of that coresight component. The latter clock
  55           is optional.
  56
  57         * port or ports: The representation of the component's port
  58           layout using the generic DT graph presentation found in
  59           "bindings/graph.txt".
  60
  61 * Additional required properties for System Trace Macrocells (STM):
  62         * reg: along with the physical base address and length of the register
  63           set as described above, another entry is required to describe the
  64           mapping of the extended stimulus port area.
  65
  66         * reg-names: the only acceptable values are "stm-base" and
  67           "stm-stimulus-base", each corresponding to the areas defined in "reg".
  68
  69 * Required properties for devices that don't show up on the AMBA bus, such as
  70   non-configurable replicators:
  71
  72         * compatible: Currently supported value is (note the absence of the
  73           AMBA markee):
  74                 - "arm,coresight-replicator"
  75
  76         * port or ports: same as above.
  77
  78 * Optional properties for ETM/PTMs:
  79
  80         * arm,cp14: must be present if the system accesses ETM/PTM management
  81           registers via co-processor 14.
  82
  83         * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
  84           source is considered to belong to CPU0.
  85
  86 * Optional property for TMC:
  87
  88         * arm,buffer-size: size of contiguous buffer space for TMC ETR
  89           (embedded trace router). This property is obsolete. The buffer size
  90           can be configured dynamically via buffer_size property in sysfs.
  91
  92         * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
  93           use the SG mode on this system.
  94
  95 * Optional property for CATU :
  96         * interrupts : Exactly one SPI may be listed for reporting the address
  97           error
  98
  99 Example:
 100
 101 1. Sinks
 102         etb@20010000 {
 103                 compatible = "arm,coresight-etb10", "arm,primecell";
 104                 reg = <0 0x20010000 0 0x1000>;
 105
 106                 clocks = <&oscclk6a>;
 107                 clock-names = "apb_pclk";
 108                 port {
 109                         etb_in_port: endpoint@0 {
 110                                 slave-mode;
 111                                 remote-endpoint = <&replicator_out_port0>;
 112                         };
 113                 };
 114         };
 115
 116         tpiu@20030000 {
 117                 compatible = "arm,coresight-tpiu", "arm,primecell";
 118                 reg = <0 0x20030000 0 0x1000>;
 119
 120                 clocks = <&oscclk6a>;
 121                 clock-names = "apb_pclk";
 122                 port {
 123                         tpiu_in_port: endpoint@0 {
 124                                 slave-mode;
 125                                 remote-endpoint = <&replicator_out_port1>;
 126                         };
 127                 };
 128         };
 129
 130         etr@20070000 {
 131                 compatible = "arm,coresight-tmc", "arm,primecell";
 132                 reg = <0 0x20070000 0 0x1000>;
 133
 134                 clocks = <&oscclk6a>;
 135                 clock-names = "apb_pclk";
 136                 ports {
 137                         #address-cells = <1>;
 138                         #size-cells = <0>;
 139
 140                         /* input port */
 141                         port@0 {
 142                                 reg =  <0>;
 143                                 etr_in_port: endpoint {
 144                                         slave-mode;
 145                                         remote-endpoint = <&replicator2_out_port0>;
 146                                 };
 147                         };
 148
 149                         /* CATU link represented by output port */
 150                         port@1 {
 151                                 reg = <1>;
 152                                 etr_out_port: endpoint {
 153                                         remote-endpoint = <&catu_in_port>;
 154                                 };
 155                         };
 156                 };
 157         };
 158
 159 2. Links
 160         replicator {
 161                 /* non-configurable replicators don't show up on the
 162                  * AMBA bus.  As such no need to add "arm,primecell".
 163                  */
 164                 compatible = "arm,coresight-replicator";
 165
 166                 ports {
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169
 170                         /* replicator output ports */
 171                         port@0 {
 172                                 reg = <0>;
 173                                 replicator_out_port0: endpoint {
 174                                         remote-endpoint = <&etb_in_port>;
 175                                 };
 176                         };
 177
 178                         port@1 {
 179                                 reg = <1>;
 180                                 replicator_out_port1: endpoint {
 181                                         remote-endpoint = <&tpiu_in_port>;
 182                                 };
 183                         };
 184
 185                         /* replicator input port */
 186                         port@2 {
 187                                 reg = <0>;
 188                                 replicator_in_port0: endpoint {
 189                                         slave-mode;
 190                                         remote-endpoint = <&funnel_out_port0>;
 191                                 };
 192                         };
 193                 };
 194         };
 195
 196         funnel@20040000 {
 197                 compatible = "arm,coresight-funnel", "arm,primecell";
 198                 reg = <0 0x20040000 0 0x1000>;
 199
 200                 clocks = <&oscclk6a>;
 201                 clock-names = "apb_pclk";
 202                 ports {
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205
 206                         /* funnel output port */
 207                         port@0 {
 208                                 reg = <0>;
 209                                 funnel_out_port0: endpoint {
 210                                         remote-endpoint =
 211                                                         <&replicator_in_port0>;
 212                                 };
 213                         };
 214
 215                         /* funnel input ports */
 216                         port@1 {
 217                                 reg = <0>;
 218                                 funnel_in_port0: endpoint {
 219                                         slave-mode;
 220                                         remote-endpoint = <&ptm0_out_port>;
 221                                 };
 222                         };
 223
 224                         port@2 {
 225                                 reg = <1>;
 226                                 funnel_in_port1: endpoint {
 227                                         slave-mode;
 228                                         remote-endpoint = <&ptm1_out_port>;
 229                                 };
 230                         };
 231
 232                         port@3 {
 233                                 reg = <2>;
 234                                 funnel_in_port2: endpoint {
 235                                         slave-mode;
 236                                         remote-endpoint = <&etm0_out_port>;
 237                                 };
 238                         };
 239
 240                 };
 241         };
 242
 243 3. Sources
 244         ptm@2201c000 {
 245                 compatible = "arm,coresight-etm3x", "arm,primecell";
 246                 reg = <0 0x2201c000 0 0x1000>;
 247
 248                 cpu = <&cpu0>;
 249                 clocks = <&oscclk6a>;
 250                 clock-names = "apb_pclk";
 251                 port {
 252                         ptm0_out_port: endpoint {
 253                                 remote-endpoint = <&funnel_in_port0>;
 254                         };
 255                 };
 256         };
 257
 258         ptm@2201d000 {
 259                 compatible = "arm,coresight-etm3x", "arm,primecell";
 260                 reg = <0 0x2201d000 0 0x1000>;
 261
 262                 cpu = <&cpu1>;
 263                 clocks = <&oscclk6a>;
 264                 clock-names = "apb_pclk";
 265                 port {
 266                         ptm1_out_port: endpoint {
 267                                 remote-endpoint = <&funnel_in_port1>;
 268                         };
 269                 };
 270         };
 271
 272 4. STM
 273         stm@20100000 {
 274                 compatible = "arm,coresight-stm", "arm,primecell";
 275                 reg = <0 0x20100000 0 0x1000>,
 276                       <0 0x28000000 0 0x180000>;
 277                 reg-names = "stm-base", "stm-stimulus-base";
 278
 279                 clocks = <&soc_smc50mhz>;
 280                 clock-names = "apb_pclk";
 281                 port {
 282                         stm_out_port: endpoint {
 283                                 remote-endpoint = <&main_funnel_in_port2>;
 284                         };
 285                 };
 286         };
 287
 288 5. CATU
 289
 290         catu@207e0000 {
 291                 compatible = "arm,coresight-catu", "arm,primecell";
 292                 reg = <0 0x207e0000 0 0x1000>;
 293
 294                 clocks = <&oscclk6a>;
 295                 clock-names = "apb_pclk";
 296
 297                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 298                 port {
 299                         catu_in_port: endpoint {
 300                                 slave-mode;
 301                                 remote-endpoint = <&etr_out_port>;
 302                         };
 303                 };
 304         };
 305
 306 [1]. There is currently two version of STM: STM32 and STM500.  Both
 307 have the same HW interface and as such don't need an explicit binding name.