Documentation/devicetree/bindings/arm/atmel-at91.txt

   1 Atmel AT91 device tree bindings.
   2 ================================
   3
   4 Boards with a SoC of the Atmel AT91 or SMART family shall have the following
   5 properties:
   6
   7 Required root node properties:
   8 compatible: must be one of:
   9  * "atmel,at91rm9200"
  10
  11  * "atmel,at91sam9" for SoCs using an ARM926EJ-S core, shall be extended with
  12    the specific SoC family or compatible:
  13     o "atmel,at91sam9260"
  14     o "atmel,at91sam9261"
  15     o "atmel,at91sam9263"
  16     o "atmel,at91sam9x5" for the 5 series, shall be extended with the specific
  17       SoC compatible:
  18        - "atmel,at91sam9g15"
  19        - "atmel,at91sam9g25"
  20        - "atmel,at91sam9g35"
  21        - "atmel,at91sam9x25"
  22        - "atmel,at91sam9x35"
  23     o "atmel,at91sam9g20"
  24     o "atmel,at91sam9g45"
  25     o "atmel,at91sam9n12"
  26     o "atmel,at91sam9rl"
  27  * "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
  28    SoC family:
  29     o "atmel,sama5d3" shall be extended with the specific SoC compatible:
  30        - "atmel,sama5d31"
  31        - "atmel,sama5d33"
  32        - "atmel,sama5d34"
  33        - "atmel,sama5d35"
  34        - "atmel,sama5d36"
  35     o "atmel,sama5d4" shall be extended with the specific SoC compatible:
  36        - "atmel,sama5d41"
  37        - "atmel,sama5d42"
  38        - "atmel,sama5d43"
  39        - "atmel,sama5d44"
  40
  41 PIT Timer required properties:
  42 - compatible: Should be "atmel,at91sam9260-pit"
  43 - reg: Should contain registers location and length
  44 - interrupts: Should contain interrupt for the PIT which is the IRQ line
  45   shared across all System Controller members.
  46
  47 System Timer (ST) required properties:
  48 - compatible: Should be "atmel,at91rm9200-st"
  49 - reg: Should contain registers location and length
  50 - interrupts: Should contain interrupt for the ST which is the IRQ line
  51   shared across all System Controller members.
  52
  53 TC/TCLIB Timer required properties:
  54 - compatible: Should be "atmel,<chip>-tcb".
  55   <chip> can be "at91rm9200" or "at91sam9x5"
  56 - reg: Should contain registers location and length
  57 - interrupts: Should contain all interrupts for the TC block
  58   Note that you can specify several interrupt cells if the TC
  59   block has one interrupt per channel.
  60 - clock-names: tuple listing input clock names.
  61         Required elements: "t0_clk"
  62         Optional elements: "t1_clk", "t2_clk"
  63 - clocks: phandles to input clocks.
  64
  65 Examples:
  66
  67 One interrupt per TC block:
  68         tcb0: timer@fff7c000 {
  69                 compatible = "atmel,at91rm9200-tcb";
  70                 reg = <0xfff7c000 0x100>;
  71                 interrupts = <18 4>;
  72                 clocks = <&tcb0_clk>;
  73                 clock-names = "t0_clk";
  74         };
  75
  76 One interrupt per TC channel in a TC block:
  77         tcb1: timer@fffdc000 {
  78                 compatible = "atmel,at91rm9200-tcb";
  79                 reg = <0xfffdc000 0x100>;
  80                 interrupts = <26 4 27 4 28 4>;
  81                 clocks = <&tcb1_clk>;
  82                 clock-names = "t0_clk";
  83         };
  84
  85 RSTC Reset Controller required properties:
  86 - compatible: Should be "atmel,<chip>-rstc".
  87   <chip> can be "at91sam9260" or "at91sam9g45"
  88 - reg: Should contain registers location and length
  89
  90 Example:
  91
  92         rstc@fffffd00 {
  93                 compatible = "atmel,at91sam9260-rstc";
  94                 reg = <0xfffffd00 0x10>;
  95         };
  96
  97 RAMC SDRAM/DDR Controller required properties:
  98 - compatible: Should be "atmel,at91rm9200-sdramc",
  99                         "atmel,at91sam9260-sdramc",
 100                         "atmel,at91sam9g45-ddramc",
 101                         "atmel,sama5d3-ddramc",
 102 - reg: Should contain registers location and length
 103
 104 Examples:
 105
 106         ramc0: ramc@ffffe800 {
 107                 compatible = "atmel,at91sam9g45-ddramc";
 108                 reg = <0xffffe800 0x200>;
 109         };
 110
 111 SHDWC Shutdown Controller
 112
 113 required properties:
 114 - compatible: Should be "atmel,<chip>-shdwc".
 115   <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
 116 - reg: Should contain registers location and length
 117
 118 optional properties:
 119 - atmel,wakeup-mode: String, operation mode of the wakeup mode.
 120   Supported values are: "none", "high", "low", "any".
 121 - atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
 122
 123 optional at91sam9260 properties:
 124 - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
 125
 126 optional at91sam9rl properties:
 127 - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
 128 - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
 129
 130 optional at91sam9x5 properties:
 131 - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
 132
 133 Example:
 134
 135         rstc@fffffd00 {
 136                 compatible = "atmel,at91sam9260-rstc";
 137                 reg = <0xfffffd00 0x10>;
 138         };