plugins/wimax/msg_reg_req.c

   1 /* msg_reg_req.c
   2  * WiMax MAC Management REG-REQ Message decoder
   3  *
   4  * Copyright (c) 2007 by Intel Corporation.
   5  *
   6  * Author: John R. Underwood <junderx@yahoo.com>
   7  *
   8  * $Id$
   9  *
  10  * Wireshark - Network traffic analyzer
  11  * By Gerald Combs <gerald@wireshark.org>
  12  * Copyright 1999 Gerald Combs
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  27  */
  28
  29 /* Include files */
  30
  31 #ifdef HAVE_CONFIG_H
  32 #include "config.h"
  33 #endif
  34
  35 #define WIMAX_16E_2005
  36
  37 #include "moduleinfo.h"
  38
  39 #include <glib.h>
  40 #include <epan/packet.h>
  41 #include "crc.h"
  42 #include "wimax_tlv.h"
  43 #include "wimax_mac.h"
  44 #include "wimax_utils.h"
  45
  46 extern gint proto_wimax;
  47 extern gboolean include_cor2_changes;
  48
  49 /* Forward reference */
  50 void dissect_mac_mgmt_msg_reg_req_decoder(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree);
  51
  52
  53 gint proto_mac_mgmt_msg_reg_req_decoder = -1;
  54 static gint ett_mac_mgmt_msg_reg_req_decoder = -1;
  55
  56 /* Setup protocol subtree array */
  57 static gint *ett[] =
  58 {
  59         &ett_mac_mgmt_msg_reg_req_decoder
  60 };
  61
  62 /* REG-REQ fields */
  63 static gint hf_reg_ss_mgmt_support                   = -1;
  64 static gint hf_reg_ip_mgmt_mode                      = -1;
  65 static gint hf_reg_ip_version                        = -1;
  66 static gint hf_reg_req_secondary_mgmt_cid            = -1;
  67 static gint hf_reg_ul_cids                           = -1;
  68 static gint hf_reg_max_classifiers                   = -1;
  69 static gint hf_reg_phs                               = -1;
  70 static gint hf_reg_arq                               = -1;
  71 static gint hf_reg_dsx_flow_control                  = -1;
  72 static gint hf_reg_mac_crc_support                   = -1;
  73 static gint hf_reg_mca_flow_control                  = -1;
  74 static gint hf_reg_mcast_polling_cids                = -1;
  75 static gint hf_reg_num_dl_trans_cid                  = -1;
  76 static gint hf_reg_mac_address                       = -1;
  77 static gint hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame      = -1;
  78 static gint hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame      = -1;
  79 static gint hf_reg_tlv_t_21_packing_support                        = -1;
  80 static gint hf_reg_tlv_t_22_mac_extended_rtps_support              = -1;
  81 static gint hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms = -1;
  82 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp     = -1;
  83 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4 = -1;
  84 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6   = -1;
  85 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6     = -1;
  86 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd     = -1;
  87 static gint hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable          = -1;
  88 static gint hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps = -1;
  89 static gint hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map = -1;
  90 static gint hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps       = -1;
  91 static gint hf_reg_tlv_t_27_handover_mdho_ul_multiple              = -1;
  92 static gint hf_reg_tlv_t_27_handover_reserved                      = -1;
  93 static gint hf_reg_tlv_t_29_ho_process_opt_ms_timer                = -1;
  94 static gint hf_reg_tlv_t_31_mobility_handover                      = -1;
  95 static gint hf_reg_tlv_t_31_mobility_sleep_mode                    = -1;
  96 static gint hf_reg_tlv_t_31_mobility_idle_mode                     = -1;
  97 static gint hf_reg_req_tlv_t_32_sleep_mode_recovery_time           = -1;
  98 static gint hf_ms_previous_ip_address_v4                           = -1;
  99 static gint hf_ms_previous_ip_address_v6                           = -1;
 100 static gint hf_idle_mode_timeout                                   = -1;
 101 static gint hf_reg_req_tlv_t_45_ms_periodic_ranging_timer          = -1;
 102 static gint hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry = -1;
 103 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry = -1;
 104 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry = -1;
 105 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack = -1;
 106 static gint hf_reg_tlv_t_40_arq_ack_type_reserved                  = -1;
 107 static gint hf_reg_tlv_t_41_ho_connections_param_processing_time   = -1;
 108 static gint hf_reg_tlv_t_42_ho_tek_processing_time                 = -1;
 109 static gint hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support = -1;
 110 static gint hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support = -1;
 111 static gint hf_reg_tlv_t_43_cqich_allocation_request_header_support = -1;
 112 static gint hf_reg_tlv_t_43_phy_channel_report_header_support      = -1;
 113 static gint hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support = -1;
 114 static gint hf_reg_tlv_t_43_sn_report_header_support               = -1;
 115 static gint hf_reg_tlv_t_43_feedback_header_support                = -1;
 116 static gint hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter = -1;
 117 static gint hf_reg_tlv_t_43_sdu_sn_parameter                       = -1;
 118 static gint hf_reg_tlv_t_43_dl_sleep_control_extended_subheader    = -1;
 119 static gint hf_reg_tlv_t_43_feedback_request_extended_subheader    = -1;
 120 static gint hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader  = -1;
 121 static gint hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader  = -1;
 122 static gint hf_reg_tlv_t_43_mini_feedback_extended_subheader       = -1;
 123 static gint hf_reg_tlv_t_43_sn_request_extended_subheader          = -1;
 124 static gint hf_reg_tlv_t_43_pdu_sn_short_extended_subheader        = -1;
 125 static gint hf_reg_tlv_t_43_pdu_sn_long_extended_subheader         = -1;
 126 static gint hf_reg_tlv_t_43_reserved                               = -1;
 127 static gint hf_reg_tlv_t_46_handover_indication_readiness_timer    = -1;
 128 static gint hf_reg_req_min_time_for_intra_fa                       = -1;
 129 static gint hf_reg_req_min_time_for_inter_fa                       = -1;
 130 static gint hf_reg_encap_atm_4                                     = -1;
 131 static gint hf_reg_encap_ipv4_4                                      = -1;
 132 static gint hf_reg_encap_ipv6_4                                      = -1;
 133 static gint hf_reg_encap_802_3_4                                     = -1;
 134 static gint hf_reg_encap_802_1q_4                                    = -1;
 135 static gint hf_reg_encap_ipv4_802_3_4                                = -1;
 136 static gint hf_reg_encap_ipv6_802_3_4                                = -1;
 137 static gint hf_reg_encap_ipv4_802_1q_4                               = -1;
 138 static gint hf_reg_encap_ipv6_802_1q_4                               = -1;
 139 static gint hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4  = -1;
 140 static gint hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4 = -1;
 141 static gint hf_reg_encap_packet_ip_rohc_header_compression_4         = -1;
 142 static gint hf_reg_encap_packet_ip_ecrtp_header_compression_4        = -1;
 143 static gint hf_reg_encap_rsvd_4                                     = -1;
 144 static gint hf_reg_encap_atm_2                                     = -1;
 145 static gint hf_reg_encap_ipv4_2                                      = -1;
 146 static gint hf_reg_encap_ipv6_2                                      = -1;
 147 static gint hf_reg_encap_802_3_2                                     = -1;
 148 static gint hf_reg_encap_802_1q_2                                    = -1;
 149 static gint hf_reg_encap_ipv4_802_3_2                                = -1;
 150 static gint hf_reg_encap_ipv6_802_3_2                                = -1;
 151 static gint hf_reg_encap_ipv4_802_1q_2                               = -1;
 152 static gint hf_reg_encap_ipv6_802_1q_2                               = -1;
 153 static gint hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2  = -1;
 154 static gint hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2 = -1;
 155 static gint hf_reg_encap_packet_ip_rohc_header_compression_2         = -1;
 156 static gint hf_reg_encap_packet_ip_ecrtp_header_compression_2        = -1;
 157 static gint hf_reg_encap_rsvd_2                                     = -1;
 158 static gint hf_tlv_type                                            = -1;
 159 static gint hf_reg_invalid_tlv                                     = -1;
 160 static gint hf_reg_power_saving_class_type_i                       = -1;
 161 static gint hf_reg_power_saving_class_type_ii                      = -1;
 162 static gint hf_reg_power_saving_class_type_iii                     = -1;
 163 static gint hf_reg_multi_active_power_saving_classes               = -1;
 164 static gint hf_reg_total_power_saving_class_instances              = -1;
 165 static gint hf_reg_power_saving_class_reserved                     = -1;
 166
 167 static gint hf_reg_req_message_type                                = -1;
 168
 169 /* STRING RESOURCES */
 170
 171 static const true_false_string tfs_reg_ip_mgmt_mode = {
 172     "IP-managed mode",
 173     "Unmanaged mode"
 174 };
 175
 176 static const true_false_string tfs_reg_ss_mgmt_support = {
 177     "secondary management connection",
 178     "no secondary management connection"
 179 };
 180
 181 static const true_false_string tfs_arq_enable = {
 182             "ARQ Requested/Accepted",
 183                 "ARQ Not Requested/Accepted"
 184 };
 185
 186 static const true_false_string tfs_arq_deliver_in_order = {
 187             "Order of delivery is preserved",
 188                 "Order of delivery is not preserved"
 189 };
 190
 191 static const true_false_string tfs_reg_fbss_mdho_ho_disable = {
 192     "Disable",
 193     "Enable"
 194 };
 195
 196 static const value_string vals_reg_ip_version[] = {
 197     {0x1,                               "IPv4"},
 198     {0x2,                               "IPV6"},
 199     {0,                                 NULL}
 200 };
 201
 202 static const value_string vals_reg_phs_support[] = {
 203     {0,                                 "no PHS support"},
 204     {1,                                 "ATM PHS"},
 205     {2,                                 "Packet PHS"},
 206     {3,                                 "ATM and Packet PHS"},
 207     {0,                                 NULL}
 208 };
 209
 210 static const true_false_string tfs_supported = {
 211     "supported",
 212     "unsupported"
 213 };
 214
 215 static const true_false_string tfs_mac_crc_support = {
 216     "MAC CRC Support (Default)",
 217     "No MAC CRC Support"
 218 };
 219
 220 static const value_string tfs_support[] = {
 221     {0,                                 "not supported"},
 222     {1,                                 "supported"},
 223     {0,                                 NULL}
 224 };
 225
 226 /* REG-REQ fields display */
 227 static hf_register_info hf[] =
 228 {
 229         {
 230                 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp,
 231                 {
 232                         "DHCP", "wmx.reg.alloc_sec_mgmt_dhcp",
 233                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, "", HFILL
 234                 }
 235         },
 236         {
 237                 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6,
 238                 {
 239                         "DHCPv6", "wmx.reg.alloc_sec_mgmt_dhcpv6",
 240                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, "", HFILL
 241                 }
 242         },
 243         {
 244                 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6,
 245                 {
 246                         "IPv6 Stateless Address Autoconfiguration", "wmx.reg.alloc_sec_mgmt_ipv6",
 247                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, "", HFILL
 248                 }
 249         },
 250         {
 251                 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4,
 252                 {
 253                         "Mobile IPv4", "wmx.reg.alloc_sec_mgmt_mobile_ipv4",
 254                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, "", HFILL
 255                 }
 256         },
 257         {
 258                 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd,
 259                 {
 260                         "Reserved", "wmx.reg.alloc_sec_mgmt_rsvd",
 261                         FT_UINT8, BASE_DEC, NULL, 0xF0, "", HFILL
 262                 }
 263         },
 264         {
 265                 &hf_reg_arq,
 266                 {
 267                         "ARQ support", "wmx.reg.arq",
 268                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x0, "", HFILL
 269                 }
 270         },
 271         {
 272                 &hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry,
 273                 {
 274                         "Cumulative ACK entry", "wmx.reg.arq_ack_type_cumulative_ack_entry",
 275                         FT_UINT8, BASE_DEC, NULL, 0x2, "", HFILL
 276                 }
 277         },
 278         {
 279                 &hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack,
 280                 {
 281                         "Cumulative ACK with Block Sequence ACK", "wmx.reg.arq_ack_type_cumulative_ack_with_block_sequence_ack",
 282                         FT_UINT8, BASE_DEC, NULL, 0x8, "", HFILL
 283                 }
 284         },
 285         {
 286                 &hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry,
 287                 {
 288                         "Cumulative with Selective ACK entry", "wmx.reg.arq_ack_type_cumulative_with_selective_ack_entry",
 289                         FT_UINT8, BASE_DEC, NULL, 0x4, "", HFILL
 290                 }
 291         },
 292         {
 293                 &hf_reg_tlv_t_40_arq_ack_type_reserved,
 294                 {
 295                         "Reserved", "wmx.reg.arq_ack_type_reserved",
 296                         FT_UINT8, BASE_DEC, NULL, 0xf0, "", HFILL
 297                 }
 298         },
 299         {
 300                 &hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry,
 301                 {
 302                         "Selective ACK entry", "wmx.reg.arq_ack_type_selective_ack_entry",
 303                         FT_UINT8, BASE_DEC, NULL, 0x1, "", HFILL
 304                 }
 305         },
 306         {
 307                 &hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support,
 308                 {
 309                         "Bandwidth request and CINR report header support", "wmx.reg.bandwidth_request_cinr_report_header_support",
 310                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x2, "", HFILL
 311                 }
 312         },
 313         {
 314                 &hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support,
 315                 {
 316                         "Bandwidth request and uplink sleep control header support", "wmx.reg.bandwidth_request_ul_sleep_control_header_support",
 317                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x10, "", HFILL
 318                 }
 319         },
 320         {
 321                 &hf_reg_tlv_t_43_cqich_allocation_request_header_support,
 322                 {
 323                         "CQICH Allocation Request header support", "wmx.reg.cqich_allocation_request_header_support",
 324                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x4, "", HFILL
 325                 }
 326         },
 327         {
 328                 &hf_reg_tlv_t_43_dl_sleep_control_extended_subheader,
 329                 {
 330                         "Downlink sleep control extended subheader", "wmx.reg.dl_sleep_control_extended_subheader",
 331                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x800, "", HFILL
 332                 }
 333         },
 334         {
 335                 &hf_reg_dsx_flow_control,
 336                 {
 337                         "DSx flow control", "wmx.reg.dsx_flow_control",
 338                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 339                 }
 340         },
 341         /* When REG-REQ TLV 7 is length 2 */
 342         {
 343                 &hf_reg_encap_802_1q_2,
 344                 {
 345                         "Packet, 802.1Q VLAN", "wmx.reg.encap_802_1q",
 346                         FT_UINT16, BASE_HEX, NULL, 0x0010, "", HFILL
 347                 }
 348         },
 349         {
 350                 &hf_reg_encap_802_3_2,
 351                 {
 352                         "Packet, 802.3/Ethernet", "wmx.reg.encap_802_3",
 353                         FT_UINT16, BASE_HEX, NULL, 0x00000008, "", HFILL
 354                 }
 355         },
 356         {
 357                 &hf_reg_encap_atm_2,
 358                 {
 359                         "ATM", "wmx.reg.encap_atm",
 360                         FT_UINT16, BASE_HEX, NULL, 0x00000001, "", HFILL
 361                 }
 362         },
 363         {
 364                 &hf_reg_encap_ipv4_2,
 365                 {
 366                         "Packet, IPv4", "wmx.reg.encap_ipv4",
 367                         FT_UINT16, BASE_HEX, NULL, 0x00000002, "", HFILL
 368                 }
 369         },
 370         {
 371                 &hf_reg_encap_ipv6_2,
 372                 {
 373                         "Packet, IPv6", "wmx.reg.encap_ipv6",
 374                         FT_UINT16, BASE_HEX, NULL, 0x00000004, "", HFILL
 375                 }
 376         },
 377         {
 378                 &hf_reg_encap_ipv4_802_1q_2,
 379                 {
 380                         "Packet, IPv4 over 802.1Q VLAN", "wmx.reg.encap_ipv4_802_1q",
 381                         FT_UINT16, BASE_HEX, NULL, 0x00000080, "", HFILL
 382                 }
 383         },
 384         {
 385                 &hf_reg_encap_ipv4_802_3_2,
 386                 {
 387                         "Packet, IPv4 over 802.3/Ethernet", "wmx.reg.encap_ipv4_802_3",
 388                         FT_UINT16, BASE_HEX, NULL, 0x00000020, "", HFILL
 389                 }
 390         },
 391         {
 392                 &hf_reg_encap_ipv6_802_1q_2,
 393                 {
 394                         "Packet, IPv6 over 802.1Q VLAN", "wmx.reg.encap_ipv6_802_1q",
 395                         FT_UINT16, BASE_HEX, NULL, 0x00000100, "", HFILL
 396                 }
 397         },
 398         {
 399                 &hf_reg_encap_ipv6_802_3_2,
 400                 {
 401                         "Packet, IPv6 over 802.3/Ethernet", "wmx.reg.encap_ipv6_802_3",
 402                         FT_UINT16, BASE_HEX, NULL, 0x00000040, "", HFILL
 403                 }
 404         },
 405         {
 406                 &hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2,
 407                 {
 408                         "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ECRTP header compression", "wmx.reg.encap_packet_802_3_ethernet_and_ecrtp_header_compression",
 409                         FT_UINT16, BASE_HEX, NULL, 0x00000400, "", HFILL
 410                 }
 411         },
 412         {
 413                 &hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2,
 414                 {
 415                         "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ROHC header compression", "wmx.reg.encap_packet_802_3_ethernet_and_rohc_header_compression",
 416                         FT_UINT16, BASE_HEX, NULL, 0x00000200, "", HFILL
 417                 }
 418         },
 419         {
 420                 &hf_reg_encap_packet_ip_ecrtp_header_compression_2,
 421                 {
 422                         "Packet, IP (v4 or v6) with ECRTP header compression", "wmx.reg.encap_packet_ip_ecrtp_header_compression",
 423                         FT_UINT16, BASE_HEX, NULL, 0x00001000, "", HFILL
 424                 }
 425         },
 426         {
 427                 &hf_reg_encap_packet_ip_rohc_header_compression_2,
 428                 {
 429                         "Packet, IP (v4 or v6) with ROHC header compression", "wmx.reg.encap_packet_ip_rohc_header_compression",
 430                         FT_UINT16, BASE_HEX, NULL, 0x00000800, "", HFILL
 431                 }
 432         },
 433         {
 434                 &hf_reg_encap_rsvd_2,
 435                 {
 436                         "Reserved", "wmx.reg.encap_rsvd",
 437                         FT_UINT16, BASE_HEX, NULL, 0x0000E000, "", HFILL
 438                 }
 439         },
 440         /* When REG-REQ TLV 7 is length 4 */
 441         {
 442                 &hf_reg_encap_802_1q_4,
 443                 {
 444                         "Packet, 802.1Q VLAN", "wmx.reg.encap_802_1q",
 445                         FT_UINT32, BASE_HEX, NULL, 0x0010, "", HFILL
 446                 }
 447         },
 448         {
 449                 &hf_reg_encap_802_3_4,
 450                 {
 451                         "Packet, 802.3/Ethernet", "wmx.reg.encap_802_3",
 452                         FT_UINT32, BASE_HEX, NULL, 0x00000008, "", HFILL
 453                 }
 454         },
 455         {
 456                 &hf_reg_encap_atm_4,
 457                 {
 458                         "ATM", "wmx.reg.encap_atm",
 459                         FT_UINT32, BASE_HEX, NULL, 0x00000001, "", HFILL
 460                 }
 461         },
 462         {
 463                 &hf_reg_encap_ipv4_4,
 464                 {
 465                         "Packet, IPv4", "wmx.reg.encap_ipv4",
 466                         FT_UINT32, BASE_HEX, NULL, 0x00000002, "", HFILL
 467                 }
 468         },
 469         {
 470                 &hf_reg_encap_ipv4_802_1q_4,
 471                 {
 472                         "Packet, IPv4 over 802.1Q VLAN", "wmx.reg.encap_ipv4_802_1q",
 473                         FT_UINT32, BASE_HEX, NULL, 0x00000080, "", HFILL
 474                 }
 475         },
 476         {
 477                 &hf_reg_encap_ipv4_802_3_4,
 478                 {
 479                         "Packet, IPv4 over 802.3/Ethernet", "wmx.reg.encap_ipv4_802_3",
 480                         FT_UINT32, BASE_HEX, NULL, 0x00000020, "", HFILL
 481                 }
 482         },
 483         {
 484                 &hf_reg_encap_ipv6_4,
 485                 {
 486                         "Packet, IPv6", "wmx.reg.encap_ipv6",
 487                         FT_UINT32, BASE_HEX, NULL, 0x00000004, "", HFILL
 488                 }
 489         },
 490         {
 491                 &hf_reg_encap_ipv6_802_1q_4,
 492                 {
 493                         "Packet, IPv6 over 802.1Q VLAN", "wmx.reg.encap_ipv6_802_1q",
 494                         FT_UINT32, BASE_HEX, NULL, 0x00000100, "", HFILL
 495                 }
 496         },
 497         {
 498                 &hf_reg_encap_ipv6_802_3_4,
 499                 {
 500                         "Packet, IPv6 over 802.3/Ethernet", "wmx.reg.encap_ipv6_802_3",
 501                         FT_UINT32, BASE_HEX, NULL, 0x00000040, "", HFILL
 502                 }
 503         },
 504         {
 505                 &hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4,
 506                 {
 507                         "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ECRTP header compression", "wmx.reg.encap_packet_802_3_ethernet_and_ecrtp_header_compression",
 508                         FT_UINT32, BASE_HEX, NULL, 0x00000400, "", HFILL
 509                 }
 510         },
 511         {
 512                 &hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4,
 513                 {
 514                         "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ROHC header compression", "wmx.reg.encap_packet_802_3_ethernet_and_rohc_header_compression",
 515                         FT_UINT32, BASE_HEX, NULL, 0x00000200, "", HFILL
 516                 }
 517         },
 518         {
 519                 &hf_reg_encap_packet_ip_ecrtp_header_compression_4,
 520                 {
 521                         "Packet, IP (v4 or v6) with ECRTP header compression", "wmx.reg.encap_packet_ip_ecrtp_header_compression",
 522                         FT_UINT32, BASE_HEX, NULL, 0x00001000, "", HFILL
 523                 }
 524         },
 525         {
 526                 &hf_reg_encap_packet_ip_rohc_header_compression_4,
 527                 {
 528                         "Packet, IP (v4 or v6) with ROHC header compression", "wmx.reg.encap_packet_ip_rohc_header_compression",
 529                         FT_UINT32, BASE_HEX, NULL, 0x00000800, "", HFILL
 530                 }
 531         },
 532         {
 533                 &hf_reg_encap_rsvd_4,
 534                 {
 535                         "Reserved", "wmx.reg.encap_rsvd",
 536                         FT_UINT32, BASE_HEX, NULL, 0xFFFFE000, "", HFILL
 537                 }
 538         },
 539         {
 540                 &hf_reg_tlv_t_22_mac_extended_rtps_support,
 541                 {
 542                         "MAC extended rtPS support", "wmx.reg.ext_rtps_support",
 543                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, "", HFILL
 544                 }
 545         },
 546         {
 547                 &hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps,
 548                 {
 549                         "FBSS/MDHO DL RF Combining with monitoring MAPs from active BSs", "wmx.reg.fbss_mdho_dl_rf_combining",
 550                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, "", HFILL
 551                 }
 552         },
 553         {
 554                 &hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support,
 555                 {
 556                         "Bandwidth request and UL Tx Power Report header support",
 557                         "wimax.reg.bandwidth_request_ul_tx_pwr_report_header_support",
 558                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x1, "", HFILL
 559                 }
 560         },
 561         {
 562                 &hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable,
 563                 {
 564                         "MDHO/FBSS HO. BS ignore all other bits when set to 1", "wmx.reg.fbss_mdho_ho_disable",
 565                         FT_BOOLEAN, 8, TFS(&tfs_reg_fbss_mdho_ho_disable), 0x01, "", HFILL
 566                 }
 567         },
 568         {
 569                 &hf_reg_tlv_t_43_feedback_header_support,
 570                 {
 571                         "Feedback header support", "wmx.reg.feedback_header_support",
 572                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x40, "", HFILL
 573                 }
 574         },
 575         {
 576                 &hf_reg_tlv_t_43_feedback_request_extended_subheader,
 577                 {
 578                         "Feedback request extended subheader", "wmx.reg.feedback_request_extended_subheader",
 579                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x1000, "", HFILL
 580                 }
 581         },
 582         {
 583                 &hf_reg_tlv_t_46_handover_indication_readiness_timer,
 584                 {
 585                         "Handover indication readiness timer", "wmx.reg.handover_indication_readiness_timer",
 586                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 587                 }
 588         },
 589         {
 590                 &hf_reg_tlv_t_27_handover_reserved,
 591                 {
 592                         "Reserved", "wmx.reg.handover_reserved",
 593                         FT_UINT8, BASE_DEC, NULL, 0xE0, "", HFILL
 594                 }
 595         },
 596         {
 597                 &hf_reg_tlv_t_41_ho_connections_param_processing_time,
 598                 {
 599                         "MS HO connections parameters processing time", "wmx.reg.ho_connections_param_processing_time",
 600                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 601                 }
 602         },
 603         {
 604                 &hf_reg_tlv_t_29_ho_process_opt_ms_timer,
 605                 {
 606                         "HO Process Optimization MS Timer", "wmx.reg.ho_process_opt_ms_timer",
 607                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 608                 }
 609         },
 610         {
 611                 &hf_reg_tlv_t_42_ho_tek_processing_time,
 612                 {
 613                         "MS HO TEK processing time", "wmx.reg.ho_tek_processing_time",
 614                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 615                 }
 616         },
 617         {
 618                 &hf_idle_mode_timeout,
 619                 {
 620                         "Idle Mode Timeout", "wmx.reg.idle_mode_timeout",
 621                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 622                 }
 623         },
 624         {
 625                 &hf_reg_ip_mgmt_mode,
 626                 {
 627                         "IP management mode", "wmx.reg.ip_mgmt_mode",
 628                         FT_BOOLEAN, 8, TFS(&tfs_reg_ip_mgmt_mode), 0x0, "", HFILL
 629                 }
 630         },
 631         {
 632                 &hf_reg_ip_version,
 633                 {
 634                         "IP version", "wmx.reg.ip_version",
 635                         FT_UINT8, BASE_HEX, VALS(vals_reg_ip_version), 0x0, "", HFILL
 636                 }
 637         },
 638         {
 639                 &hf_reg_mac_address,
 640                 {
 641                         "MAC Address of the SS", "wmx.reg.mac_address",
 642                         FT_ETHER, BASE_DEC, NULL, 0x0, "", HFILL
 643                 }
 644         },
 645         {
 646                 &hf_reg_mac_crc_support,
 647                 {
 648                         "MAC CRC", "wmx.reg.mac_crc_support",
 649                         FT_BOOLEAN, 8, TFS(&tfs_mac_crc_support), 0x0, "", HFILL
 650                 }
 651         },
 652         {
 653                 &hf_reg_max_classifiers,
 654                 {
 655                         "Maximum number of classification rules", "wmx.reg.max_classifiers",
 656                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 657                 }
 658         },
 659         {
 660                 &hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms,
 661                 {
 662                         "Maximum number of bursts transmitted concurrently to the MS", "wmx.reg.max_num_bursts_to_ms",
 663                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 664                 }
 665         },
 666         {
 667                 &hf_reg_mca_flow_control,
 668                 {
 669                         "MCA flow control", "wmx.reg.mca_flow_control",
 670                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 671                 }
 672         },
 673         {
 674                 &hf_reg_mcast_polling_cids,
 675                 {
 676                         "Multicast polling group CID support", "wmx.reg.mcast_polling_cids",
 677                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 678                 }
 679         },
 680         {
 681                 &hf_reg_tlv_t_27_handover_mdho_ul_multiple,
 682                 {
 683                         "MDHO UL Multiple transmission", "wmx.reg.mdh_ul_multiple",
 684                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x10, "", HFILL
 685                 }
 686         },
 687         {
 688                 &hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps,
 689                 {
 690                         "MDHO DL soft combining with monitoring MAPs from active BSs", "wmx.reg.mdho_dl_monitor_maps",
 691                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, "", HFILL
 692                 }
 693         },
 694         {
 695                 &hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map,
 696                 {
 697                         "MDHO DL soft Combining with monitoring single MAP from anchor BS", "wmx.reg.mdho_dl_monitor_single_map",
 698                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, "", HFILL
 699                 }
 700         },
 701         {
 702                 &hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader,
 703                 {
 704                         "MIMO mode feedback request extended subheader", "wmx.reg.mimo_mode_feedback_request_extended_subheader",
 705                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x2000, "", HFILL
 706                 }
 707         },
 708         {
 709                 &hf_reg_tlv_t_43_mini_feedback_extended_subheader,
 710                 {
 711                         "Mini-feedback extended subheader", "wmx.reg.mini_feedback_extended_subheader",
 712                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x8000, "", HFILL
 713                 }
 714         },
 715         {
 716                 &hf_reg_tlv_t_31_mobility_handover,
 717                 {
 718                         "Mobility (handover)", "wmx.reg.mobility_handover",
 719                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, "", HFILL
 720                 }
 721         },
 722         {
 723                 &hf_reg_tlv_t_31_mobility_idle_mode,
 724                 {
 725                         "Idle mode", "wmx.reg.mobility_idle_mode",
 726                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, "", HFILL
 727                 }
 728         },
 729         {
 730                 &hf_reg_tlv_t_31_mobility_sleep_mode,
 731                 {
 732                         "Sleep mode", "wmx.reg.mobility_sleep_mode",
 733                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, "", HFILL
 734                 }
 735         },
 736         {
 737                 &hf_reg_num_dl_trans_cid,
 738                 {
 739                         "Number of Downlink transport CIDs the SS can support", "wmx.reg.dl_cids_supported",
 740                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 741                 }
 742         },
 743         {
 744                 &hf_reg_tlv_t_21_packing_support,
 745                 {
 746                         "Packing support", "wmx.reg.packing.support",
 747                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, "", HFILL
 748                 }
 749         },
 750         {
 751                 &hf_reg_tlv_t_43_pdu_sn_long_extended_subheader,
 752                 {
 753                         "PDU SN (long) extended subheader", "wmx.reg.pdu_sn_long_extended_subheader",
 754                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x40000, "", HFILL
 755                 }
 756         },
 757         {
 758                 &hf_reg_tlv_t_43_pdu_sn_short_extended_subheader,
 759                 {
 760                         "PDU SN (short) extended subheader", "wmx.reg.pdu_sn_short_extended_subheader",
 761                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x20000, "", HFILL
 762                 }
 763         },
 764         {
 765                 &hf_reg_phs,
 766                 {
 767                         "PHS support", "wmx.reg.phs",
 768                         FT_UINT8, BASE_DEC, VALS(vals_reg_phs_support), 0x0, "", HFILL
 769                 }
 770         },
 771         {
 772                 &hf_reg_tlv_t_43_phy_channel_report_header_support,
 773                 {
 774                         "PHY channel report header support", "wmx.reg.phy_channel_report_header_support",
 775                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x8, "", HFILL
 776                 }
 777         },
 778         {
 779                 &hf_reg_tlv_t_43_reserved,
 780                 {
 781                         "Reserved", "wmx.reg.reserved",
 782                         FT_UINT24, BASE_DEC, NULL, 0xf80000, "", HFILL
 783                 }
 784         },
 785         {
 786                 &hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter,
 787                 {
 788                         "SDU_SN extended subheader support", "wmx.reg.sdu_sn_extended_subheader_support",
 789                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x80, "", HFILL
 790                 }
 791         },
 792         {
 793                 &hf_reg_tlv_t_43_sdu_sn_parameter,
 794                 {
 795                         "SDU_SN parameter", "wmx.reg.sdu_sn_parameter",
 796                         FT_UINT24, BASE_DEC, NULL, 0x700, "", HFILL
 797                 }
 798         },
 799         {
 800                 &hf_reg_tlv_t_43_sn_report_header_support,
 801                 {
 802                         "SN report header support", "wmx.reg.sn_report_header_support",
 803                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x20, "", HFILL
 804                 }
 805         },
 806         {
 807                 &hf_reg_tlv_t_43_sn_request_extended_subheader,
 808                 {
 809                         "SN request extended subheader", "wmx.reg.sn_request_extended_subheader",
 810                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x10000, "", HFILL
 811                 }
 812         },
 813         {
 814                 &hf_reg_ss_mgmt_support,
 815                 {
 816                         "SS management support", "wmx.reg.ss_mgmt_support",
 817                         FT_BOOLEAN, 8, TFS(&tfs_reg_ss_mgmt_support), 0x0, "", HFILL
 818                 }
 819         },
 820         {
 821                 &hf_reg_ul_cids,
 822                 {
 823                         "Number of Uplink transport CIDs the SS can support", "wmx.reg.ul_cids_supported",
 824                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 825                 }
 826         },
 827         {
 828                 &hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader,
 829                 {
 830                         "UL Tx power report extended subheader", "wmx.reg.ul_tx_power_report_extended_subheader",
 831                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x4000, "", HFILL
 832                 }
 833         },
 834         {
 835                 &hf_tlv_type,
 836                 {
 837                         "Unknown TLV Type", "wmx.reg.unknown_tlv_type",
 838                         FT_BYTES, BASE_NONE, NULL, 0x00, "", HFILL
 839                 }
 840         },
 841         {
 842                 &hf_reg_req_message_type,
 843                 {
 844                         "MAC Management Message Type", "wmx.macmgtmsgtype.reg_req",
 845                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 846                 }
 847         },
 848         {
 849                 &hf_reg_invalid_tlv,
 850                 {
 851                         "Invalid TLV", "wmx.reg_req.invalid_tlv",
 852                         FT_BYTES, BASE_HEX, NULL, 0, "", HFILL
 853                 }
 854         },
 855         {
 856                 &hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame,
 857                 {
 858                         "Maximum MAC level DL data per frame", "wmx.reg_req.max_mac_dl_data",
 859                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 860                 }
 861         },
 862         {
 863                 &hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame,
 864                 {
 865                         "Maximum MAC level UL data per frame", "wmx.reg_req.max_mac_ul_data",
 866                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 867                 }
 868         },
 869         {
 870                 &hf_reg_req_min_time_for_inter_fa,
 871                 {
 872                         "Minimum time for inter-FA HO, default=3", "wmx.reg_req.min_time_for_inter_fa",
 873                         FT_UINT8, BASE_HEX, NULL, 0xF0, "", HFILL
 874                 }
 875         },
 876         {
 877                 &hf_reg_req_min_time_for_intra_fa,
 878                 {
 879                         "Minimum time for intra-FA HO, default=2", "wmx.reg_req.min_time_for_intra_fa",
 880                         FT_UINT8, BASE_HEX, NULL, 0x0F, "", HFILL
 881                 }
 882         },
 883         {
 884                 &hf_reg_req_tlv_t_45_ms_periodic_ranging_timer,
 885                 {
 886                         "MS periodic ranging timer information", "wmx.reg_req.ms_periodic_ranging_timer_info",
 887                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 888                 }
 889         },
 890         {       /* IPv4 Mask */
 891                 &hf_ms_previous_ip_address_v4,
 892                 {
 893                         "MS Previous IP address", "wmx.reg_req.ms_prev_ip_addr_v4",
 894                         FT_IPv4, BASE_NONE, NULL, 0x0, "", HFILL
 895                 }
 896         },
 897         {       /* IPv6 Source Address */
 898                 &hf_ms_previous_ip_address_v6,
 899                 {
 900                         "MS Previous IP address", "wmx.reg_req.ms_prev_ip_addr_v6",
 901                         FT_IPv6, BASE_NONE, NULL, 0x0, "", HFILL
 902                 }
 903         },
 904         {
 905                 &hf_reg_req_secondary_mgmt_cid,
 906                 {
 907                         "Secondary Management CID", "wmx.reg_req.secondary_mgmt_cid",
 908                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 909                 }
 910         },
 911         {
 912                 &hf_reg_req_tlv_t_32_sleep_mode_recovery_time,
 913                 {
 914                         "Frames required for the MS to switch from sleep to awake-mode", "wmx.reg_req.sleep_recovery",
 915                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 916                 }
 917         },
 918         {
 919                 &hf_reg_power_saving_class_type_i,
 920                 {
 921                         "Power saving class type I supported", "wmx.reg.power_saving_class_type_i",
 922                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, "", HFILL
 923                 }
 924         },
 925         {
 926                 &hf_reg_power_saving_class_type_ii,
 927                 {
 928                         "Power saving class type II supported", "wmx.reg.power_saving_class_type_ii",
 929                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, "", HFILL
 930                 }
 931         },
 932         {
 933                 &hf_reg_power_saving_class_type_iii,
 934                 {
 935                         "Power saving class type III supported", "wmx.reg.power_saving_class_type_iii",
 936                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, "", HFILL
 937                 }
 938         },
 939         {
 940                 &hf_reg_multi_active_power_saving_classes,
 941                 {
 942                         "Multiple active power saving classes supported", "wmx.reg.multi_active_power_saving_classes",
 943                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, "", HFILL
 944                 }
 945         },
 946         {
 947                 &hf_reg_total_power_saving_class_instances,
 948                 {
 949                         "Total number of power saving class instances of all", "wmx.reg_req.total_power_saving_class_instances",
 950                         FT_UINT16, BASE_DEC, NULL, 0x1F0, "", HFILL
 951                 }
 952         },
 953         {
 954                 &hf_reg_power_saving_class_reserved,
 955                 {
 956                         "Reserved", "wmx.reg.reserved",
 957                         FT_UINT16, BASE_DEC, NULL, 0xFE00, "", HFILL
 958                 }
 959         }
 960 };
 961
 962 /* Decode REG-REQ sub-TLV's. */
 963 void dissect_extended_tlv(proto_tree *reg_req_tree, gint tlv_type, tvbuff_t *tvb, guint tlv_offset, guint tlv_len, packet_info *pinfo, guint offset, gint proto_registry)
 964 {
 965         proto_item *tlv_item = NULL;
 966         proto_tree *tlv_tree = NULL;
 967         proto_tree *sub_tree = NULL;
 968         guint tvb_len;
 969         tlv_info_t tlv_info;
 970         guint tlv_end;
 971         guint length;
 972         guint nblocks;
 973
 974         /* Get the tvb reported length */
 975         tvb_len =  tvb_reported_length(tvb);
 976
 977         /* get the TLV information */
 978         init_tlv_info(&tlv_info, tvb, offset);
 979
 980 #ifdef WIMAX_16E_2005
 981         switch (tlv_type) {
 982                 case REG_ARQ_PARAMETERS:
 983                         /* display ARQ Service Flow Encodings info */
 984                         /* add subtree */
 985                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "ARQ Service Flow Encodings (%u byte(s))", tlv_len);
 986                         /* decode and display the DL Service Flow Encodings */
 987                         wimax_service_flow_encodings_decoder(tvb_new_subset(tvb, tlv_offset, tlv_len, tlv_len), pinfo, tlv_tree);
 988                         break;
 989                 case REG_SS_MGMT_SUPPORT:
 990                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_ss_mgmt_support, tvb, tlv_offset, tlv_len, FALSE);
 991                         proto_tree_add_item(tlv_tree, hf_reg_ss_mgmt_support, tvb, tlv_offset, 1, FALSE);
 992                         break;
 993                 case REG_IP_MGMT_MODE:
 994                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_ip_mgmt_mode, tvb, tlv_offset, tlv_len, FALSE);
 995                         proto_tree_add_item(tlv_tree, hf_reg_ip_mgmt_mode, tvb, tlv_offset, 1, FALSE);
 996                         break;
 997                 case REG_IP_VERSION:
 998                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_ip_version, tvb, tlv_offset, tlv_len, FALSE);
 999                         proto_tree_add_item(tlv_tree, hf_reg_ip_version, tvb, tlv_offset, 1, FALSE);
1000                         break;
1001                 case REG_UL_TRANSPORT_CIDS_SUPPORTED:
1002                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_ul_cids, tvb, tlv_offset, tlv_len, FALSE);
1003                         proto_tree_add_item(tlv_tree, hf_reg_ul_cids, tvb, tlv_offset, tlv_len, FALSE);
1004                         break;
1005
1006                 case REG_POWER_SAVING_CLASS_CAPABILITY:
1007                         /* add TLV subtree */
1008                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Power saving class capability (%d)", tvb_get_ntohs(tvb, tlv_offset));
1009                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_i, tvb, tlv_offset, 2, FALSE);
1010                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_ii, tvb, tlv_offset, 2, FALSE);
1011                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_iii, tvb, tlv_offset, 2, FALSE);
1012                         proto_tree_add_item(tlv_tree, hf_reg_multi_active_power_saving_classes, tvb, tlv_offset, 2, FALSE);
1013                         proto_tree_add_item(tlv_tree, hf_reg_total_power_saving_class_instances, tvb, tlv_offset, 2, FALSE);
1014                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_reserved, tvb, tlv_offset, 2, FALSE);
1015                         break;
1016                 case REG_IP_PHS_SDU_ENCAP:
1017                         /* add TLV subtree */
1018                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Classification/PHS options and SDU encapsulation support 0x%04x", tvb_get_ntohs(tvb, tlv_offset));
1019
1020 #ifdef WIMAX_16E_2005
1021                         if (tlv_len == 2){
1022                                 proto_tree_add_item(tlv_tree, hf_reg_encap_atm_2, tvb, tlv_offset, tlv_len, FALSE);
1023                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_2, tvb, tlv_offset, tlv_len, FALSE);
1024                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_2, tvb, tlv_offset, tlv_len, FALSE);
1025                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_3_2, tvb, tlv_offset, tlv_len, FALSE);
1026                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_1q_2, tvb, tlv_offset, tlv_len, FALSE);
1027                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_3_2, tvb, tlv_offset, tlv_len, FALSE);
1028                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_3_2, tvb, tlv_offset, tlv_len, FALSE);
1029                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_1q_2, tvb, tlv_offset, tlv_len, FALSE);
1030                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_1q_2, tvb, tlv_offset, tlv_len, FALSE);
1031                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2, tvb, tlv_offset, tlv_len, FALSE);
1032                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2, tvb, tlv_offset, tlv_len, FALSE);
1033                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_rohc_header_compression_2, tvb, tlv_offset, tlv_len, FALSE);
1034                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_ecrtp_header_compression_2, tvb, tlv_offset, tlv_len, FALSE);
1035                                 proto_tree_add_item(tlv_tree, hf_reg_encap_rsvd_2, tvb, tlv_offset, tlv_len, FALSE);
1036                         } else if(tlv_len == 4){
1037                                 proto_tree_add_item(tlv_tree, hf_reg_encap_atm_4, tvb, tlv_offset, tlv_len, FALSE);
1038                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_4, tvb, tlv_offset, tlv_len, FALSE);
1039                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_4, tvb, tlv_offset, tlv_len, FALSE);
1040                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_3_4, tvb, tlv_offset, tlv_len, FALSE);
1041                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_1q_4, tvb, tlv_offset, tlv_len, FALSE);
1042                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_3_4, tvb, tlv_offset, tlv_len, FALSE);
1043                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_3_4, tvb, tlv_offset, tlv_len, FALSE);
1044                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_1q_4, tvb, tlv_offset, tlv_len, FALSE);
1045                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_1q_4, tvb, tlv_offset, tlv_len, FALSE);
1046                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4, tvb, tlv_offset, tlv_len, FALSE);
1047                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4, tvb, tlv_offset, tlv_len, FALSE);
1048                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_rohc_header_compression_4, tvb, tlv_offset, tlv_len, FALSE);
1049                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_ecrtp_header_compression_4, tvb, tlv_offset, tlv_len, FALSE);
1050                                 proto_tree_add_item(tlv_tree, hf_reg_encap_rsvd_4, tvb, tlv_offset, tlv_len, FALSE);
1051                         }
1052 #endif
1053                         break;
1054                 case REG_MAX_CLASSIFIERS_SUPPORTED:
1055                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_max_classifiers, tvb, tlv_offset, tlv_len, FALSE);
1056                         proto_tree_add_item(tlv_tree, hf_reg_max_classifiers, tvb, tlv_offset, 2, FALSE);
1057                         break;
1058                 case REG_PHS_SUPPORT:
1059                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_phs, tvb, tlv_offset, tlv_len, FALSE);
1060                         proto_tree_add_item(tlv_tree, hf_reg_phs, tvb, tlv_offset, 1, FALSE);
1061                         break;
1062                 case REG_ARQ_SUPPORT:
1063                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_arq, tvb, tlv_offset, tlv_len, FALSE);
1064                         proto_tree_add_item(tlv_tree, hf_reg_arq, tvb, tlv_offset, 1, FALSE);
1065                         break;
1066                 case REG_DSX_FLOW_CONTROL:
1067                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_dsx_flow_control, tvb, tlv_offset, tlv_len, FALSE);
1068                         tlv_item = proto_tree_add_item(tlv_tree, hf_reg_dsx_flow_control, tvb, tlv_offset, 1, FALSE);
1069                         if (tvb_get_guint8(tvb, tlv_offset) == 0) {
1070                                 proto_item_append_text(tlv_item, " (no limit)");
1071                         }
1072                         break;
1073                 case REG_MAC_CRC_SUPPORT:
1074                         if (!include_cor2_changes) {
1075                                 proto_tree_add_item(reg_req_tree, hf_reg_mac_crc_support, tvb, tlv_offset, 1, FALSE);
1076                                 tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_mac_crc_support, tvb, tlv_offset, tlv_len, FALSE);
1077                                 proto_tree_add_item(tlv_tree, hf_reg_mac_crc_support, tvb, tlv_offset, 1, FALSE);
1078                         } else {
1079                                 /* Unknown TLV Type */
1080                                 tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, (tvb_len - tlv_offset), FALSE);
1081                                 proto_tree_add_item(tlv_tree, hf_tlv_type, tvb, tlv_offset, (tvb_len - tlv_offset), FALSE);
1082                         }
1083                         break;
1084                 case REG_MCA_FLOW_CONTROL:
1085                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_mca_flow_control, tvb, tlv_offset, tlv_len, FALSE);
1086                         tlv_item = proto_tree_add_item(tlv_tree, hf_reg_mca_flow_control, tvb, tlv_offset, 1, FALSE);
1087                         if (tvb_get_guint8(tvb, tlv_offset) == 0) {
1088                                 proto_item_append_text(tlv_item, " (no limit)");
1089                         }
1090                         break;
1091                 case REG_MCAST_POLLING_CIDS:
1092                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_mcast_polling_cids, tvb, tlv_offset, tlv_len, FALSE);
1093                         proto_tree_add_item(tlv_tree, hf_reg_mcast_polling_cids, tvb, tlv_offset, 1, FALSE);
1094                         break;
1095                 case REG_NUM_DL_TRANS_CID:
1096                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_num_dl_trans_cid, tvb, tlv_offset, tlv_len, FALSE);
1097                         proto_tree_add_item(tlv_tree, hf_reg_num_dl_trans_cid, tvb, tlv_offset, 2, FALSE);
1098                         break;
1099                 case REG_MAC_ADDRESS:
1100                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_mac_address, tvb, tlv_offset, tlv_len, FALSE);
1101                         proto_tree_add_item(tlv_tree, hf_reg_mac_address, tvb, tlv_offset, 6, FALSE);
1102                         break;
1103                 case REG_TLV_T_20_MAX_MAC_DATA_PER_FRAME_SUPPORT:
1104                         /* display Maximum MAC level data per frame info */
1105                         /* add subtree */
1106                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Maximum MAC level data per frame (%u byte(s))", tlv_len);
1107                         /* decode and display Maximum MAC level data per frame for UL & DL */
1108                         /* Set endpoint of the subTLVs (tlv_offset + length) */
1109                         tlv_end = tlv_offset + tlv_len;
1110                         /* process subTLVs */
1111                         while ( tlv_offset < tlv_end )
1112                         {       /* get the TLV information */
1113                                 init_tlv_info(&tlv_info, tvb, tlv_offset);
1114                                 /* get the TLV type */
1115                                 tlv_type = get_tlv_type(&tlv_info);
1116                                 /* get the TLV length */
1117                                 length = get_tlv_length(&tlv_info);
1118                                 if(tlv_type == -1 || length > MAX_TLV_LEN || length < 1)
1119                                 {       /* invalid tlv info */
1120                                         if (pinfo->cinfo)
1121                                         {
1122                                                 col_append_sep_str(pinfo->cinfo, COL_INFO, NULL, "REG-REQ TLV error");
1123                                         }
1124                                         proto_tree_add_item(reg_req_tree, hf_reg_invalid_tlv, tvb, offset, (tvb_len - offset), FALSE);
1125                                         break;
1126                                 }
1127                                 /* update the offset */
1128                                 tlv_offset += get_tlv_value_offset(&tlv_info);
1129                                 nblocks = tvb_get_ntohs(tvb, tlv_offset);
1130                                 switch (tlv_type)
1131                                 {
1132                                         case REG_TLV_T_20_1_MAX_MAC_LEVEL_DATA_PER_DL_FRAME:
1133                                                 sub_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, tlv_tree, hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame, tvb, tlv_offset, length, FALSE);
1134                                                 tlv_item = proto_tree_add_item(sub_tree, hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame, tvb, tlv_offset, 2, FALSE);
1135                                                 if ( nblocks == 0 )
1136                                                 {
1137                                                         proto_item_append_text(tlv_item, " (Unlimited bytes)");
1138                                                 } else {
1139                                                         proto_item_append_text(tlv_item, " (%d bytes)", 256 * nblocks);
1140                                                 }
1141                                                 break;
1142                                         case REG_TLV_T_20_2_MAX_MAC_LEVEL_DATA_PER_UL_FRAME:
1143                                                 sub_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, tlv_tree, hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame, tvb, tlv_offset, length, FALSE);
1144                                                 tlv_item = proto_tree_add_item(sub_tree, hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame, tvb, tlv_offset, 2, FALSE);
1145                                                 if ( nblocks == 0 )
1146                                                 {
1147                                                         proto_item_append_text(tlv_item, " (Unlimited bytes)");
1148                                                 } else {
1149                                                         proto_item_append_text(tlv_item, " (%d bytes)", 256 * nblocks);
1150                                                 }
1151                                                 break;
1152                                         default:
1153                                                 sub_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, tlv_tree, hf_reg_invalid_tlv, tvb, tlv_offset, (tlv_end - tlv_offset), FALSE);
1154                                                 proto_tree_add_item(sub_tree, hf_reg_invalid_tlv, tvb, tlv_offset, (tlv_end - tlv_offset), FALSE);
1155                                                 break;
1156                                 }
1157                                 tlv_offset += length;
1158                         }
1159                         break;
1160
1161                 case REG_TLV_T_21_PACKING_SUPPORT:
1162                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_21_packing_support, tvb, tlv_offset, tlv_len, FALSE);
1163                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_21_packing_support, tvb, tlv_offset, 1, FALSE);
1164                         break;
1165                 case REG_TLV_T_22_MAC_EXTENDED_RTPS_SUPPORT:
1166                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_22_mac_extended_rtps_support, tvb, tlv_offset, tlv_len, FALSE);
1167                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_22_mac_extended_rtps_support, tvb, tlv_offset, 1, FALSE);
1168                         break;
1169                 case REG_TLV_T_23_MAX_NUM_BURSTS_TRANSMITTED_CONCURRENTLY_TO_THE_MS:
1170                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms, tvb, tlv_offset, tlv_len, FALSE);
1171                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms, tvb, tlv_offset, 1, FALSE);
1172                         break;
1173                 case REG_TLV_T_26_METHOD_FOR_ALLOCATING_IP_ADDR_SECONDARY_MGMNT_CONNECTION:
1174                         /* add TLV subtree */
1175                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Method for allocating IP address for the secondary management connection (%d)", tvb_get_guint8(tvb, tlv_offset));
1176                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp, tvb, tlv_offset, 1, FALSE);
1177                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4, tvb, tlv_offset, 1, FALSE);
1178                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6, tvb, tlv_offset, 1, FALSE);
1179                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6, tvb, tlv_offset, 1, FALSE);
1180                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd, tvb, tlv_offset, 1, FALSE);
1181                         break;
1182                 case REG_TLV_T_27_HANDOVER_SUPPORTED:
1183                         /* add TLV subtree */
1184                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Handover Support (%d)", tvb_get_guint8(tvb, tlv_offset));
1185                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable, tvb, tlv_offset, 1, FALSE);
1186                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps, tvb, tlv_offset, 1, FALSE);
1187                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map, tvb, tlv_offset, 1, FALSE);
1188                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps, tvb, tlv_offset, 1, FALSE);
1189                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_ul_multiple, tvb, tlv_offset, 1, FALSE);
1190                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_reserved, tvb, tlv_offset, 1, FALSE);
1191                         break;
1192                 case REG_TLV_T_29_HO_PROCESS_OPTIMIZATION_MS_TIMER:
1193                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_29_ho_process_opt_ms_timer, tvb, tlv_offset, tlv_len, FALSE);
1194                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_29_ho_process_opt_ms_timer, tvb, tlv_offset, 1, FALSE);
1195                         break;
1196                 case REG_TLV_T_31_MOBILITY_FEATURES_SUPPORTED:
1197                         /* add TLV subtree */
1198                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Mobility Features Supported (%d)", tvb_get_guint8(tvb, tlv_offset));
1199                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_handover, tvb, tlv_offset, 1, FALSE);
1200                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_sleep_mode, tvb, tlv_offset, 1, FALSE);
1201                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_idle_mode, tvb, tlv_offset, 1, FALSE);
1202                         break;
1203                 case REG_TLV_T_40_ARQ_ACK_TYPE:
1204                         /* add TLV subtree */
1205                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "ARQ ACK Type 0x%02x", tvb_get_guint8(tvb, tlv_offset));
1206                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry, tvb, tlv_offset, 1, FALSE);
1207                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry, tvb, tlv_offset, 1, FALSE);
1208                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry, tvb, tlv_offset, 1, FALSE);
1209                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack, tvb, tlv_offset, 1, FALSE);
1210                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_reserved, tvb, tlv_offset, 1, FALSE);
1211                         break;
1212                 case REG_TLV_T_41_MS_HO_CONNECTIONS_PARAM_PROCESSING_TIME:
1213                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_41_ho_connections_param_processing_time, tvb, tlv_offset, tlv_len, FALSE);
1214                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_41_ho_connections_param_processing_time, tvb, tlv_offset, 1, FALSE);
1215                         break;
1216                 case REG_TLV_T_42_MS_HO_TEK_PROCESSING_TIME:
1217                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_42_ho_tek_processing_time, tvb, tlv_offset, tlv_len, FALSE);
1218                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_42_ho_tek_processing_time, tvb, tlv_offset, 1, FALSE);
1219                         break;
1220                 case REG_TLV_T_43_MAC_HEADER_AND_EXTENDED_SUBHEADER_SUPPORT:
1221                         /* add TLV subtree */
1222                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "MAC header and extended subheader support %d", tvb_get_ntoh24(tvb, tlv_offset));
1223                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support, tvb, tlv_offset, 3, FALSE);
1224                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support, tvb, tlv_offset, 3, FALSE);
1225                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_cqich_allocation_request_header_support, tvb, tlv_offset, 3, FALSE);
1226                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_phy_channel_report_header_support, tvb, tlv_offset, 3, FALSE);
1227                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support, tvb, tlv_offset, 3, FALSE);
1228                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sn_report_header_support, tvb, tlv_offset, 3, FALSE);
1229                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_feedback_header_support, tvb, tlv_offset, 3, FALSE);
1230                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter, tvb, tlv_offset, 3, FALSE);
1231                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sdu_sn_parameter, tvb, tlv_offset, 3, FALSE);
1232                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_dl_sleep_control_extended_subheader, tvb, tlv_offset, 3, FALSE);
1233                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_feedback_request_extended_subheader, tvb, tlv_offset, 3, FALSE);
1234                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader, tvb, tlv_offset, 3, FALSE);
1235                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader, tvb, tlv_offset, 3, FALSE);
1236                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_mini_feedback_extended_subheader, tvb, tlv_offset, 3, FALSE);
1237                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sn_request_extended_subheader, tvb, tlv_offset, 3, FALSE);
1238                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_pdu_sn_short_extended_subheader, tvb, tlv_offset, 3, FALSE);
1239                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_pdu_sn_long_extended_subheader, tvb, tlv_offset, 3, FALSE);
1240                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_reserved, tvb, tlv_offset, 3, FALSE);
1241                         break;
1242                 case REG_REQ_BS_SWITCHING_TIMER:
1243                         /* add TLV subtree */
1244                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "BS switching timer (%d)", tvb_get_guint8(tvb, tlv_offset));
1245                         proto_tree_add_item(tlv_tree, hf_reg_req_min_time_for_intra_fa, tvb, tlv_offset, 1, FALSE);
1246                         proto_tree_add_item(tlv_tree, hf_reg_req_min_time_for_inter_fa, tvb, tlv_offset, 1, FALSE);
1247                         break;
1248                 case VENDOR_SPECIFIC_INFO:
1249                 case VENDOR_ID_ENCODING:
1250                 case CURRENT_TX_POWER:
1251                 case MAC_VERSION_ENCODING:
1252                 case CMAC_TUPLE:        /* Table 348b */
1253                         wimax_common_tlv_encoding_decoder(tvb_new_subset(tvb, offset, (tvb_len - offset), (tvb_len - offset)), pinfo, reg_req_tree);
1254                         break;
1255                 default:
1256                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, (tvb_len - tlv_offset), FALSE);
1257                         proto_tree_add_item(tlv_tree, hf_tlv_type, tvb, tlv_offset, (tvb_len - tlv_offset), FALSE);
1258                         break;
1259         }
1260 #endif
1261 }
1262
1263 /* Register Wimax Mac Payload Protocol and Dissector */
1264 void proto_register_mac_mgmt_msg_reg_req(void)
1265 {
1266         if (proto_mac_mgmt_msg_reg_req_decoder == -1)
1267         {
1268                 proto_mac_mgmt_msg_reg_req_decoder = proto_register_protocol (
1269                                                         "WiMax REG-REQ/RSP Messages", /* name */
1270                                                         "WiMax REG-REQ/RSP (reg)", /* short name */
1271                                                         "wmx.reg" /* abbrev */
1272                                                         );
1273
1274                 proto_register_field_array(proto_mac_mgmt_msg_reg_req_decoder, hf, array_length(hf));
1275                 proto_register_subtree_array(ett, array_length(ett));
1276         }
1277 }
1278
1279 /* Decode REG-REQ messages. */
1280 void dissect_mac_mgmt_msg_reg_req_decoder(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree)
1281 {
1282         guint offset = 0;
1283         guint tlv_offset;
1284         guint tvb_len, payload_type;
1285         proto_item *reg_req_item = NULL;
1286         proto_tree *reg_req_tree = NULL;
1287         proto_tree *tlv_tree = NULL;
1288         gboolean hmac_found = FALSE;
1289         tlv_info_t tlv_info;
1290         gint tlv_type;
1291         gint tlv_len;
1292
1293         /* Ensure the right payload type */
1294         payload_type = tvb_get_guint8(tvb, offset);
1295         if (payload_type != MAC_MGMT_MSG_REG_REQ)
1296         {
1297                 return;
1298         }
1299
1300         if (tree)
1301         {       /* we are being asked for details */
1302
1303                 /* Get the tvb reported length */
1304                 tvb_len =  tvb_reported_length(tvb);
1305                 /* display MAC payload type REG-REQ */
1306                 reg_req_item = proto_tree_add_protocol_format(tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tvb_len, "MAC Management Message, REG-REQ (6)");
1307                 /* add MAC REG-REQ subtree */
1308                 reg_req_tree = proto_item_add_subtree(reg_req_item, ett_mac_mgmt_msg_reg_req_decoder);
1309                 /* display the Message Type */
1310                 proto_tree_add_item(reg_req_tree, hf_reg_req_message_type, tvb, offset, 1, FALSE);
1311                 offset += 1;
1312
1313                 while(offset < tvb_len)
1314                 {
1315                         /* Get the TLV data. */
1316                         init_tlv_info(&tlv_info, tvb, offset);
1317                         /* get the TLV type */
1318                         tlv_type = get_tlv_type(&tlv_info);
1319                         /* get the TLV length */
1320                         tlv_len = get_tlv_length(&tlv_info);
1321                         if(tlv_type == -1 || tlv_len > MAX_TLV_LEN || tlv_len < 1)
1322                         {       /* invalid tlv info */
1323                                 if (pinfo->cinfo)
1324                                 {
1325                                         col_append_sep_str(pinfo->cinfo, COL_INFO, NULL, "REG-REQ TLV error");
1326                                 }
1327                                 proto_tree_add_item(reg_req_tree, hf_reg_invalid_tlv, tvb, offset, (tvb_len - offset), FALSE);
1328                                 break;
1329                         }
1330                         /* get the offset to the TLV data */
1331                         tlv_offset = offset + get_tlv_value_offset(&tlv_info);
1332
1333                         switch (tlv_type) {
1334                                 case REG_ARQ_PARAMETERS:
1335                                 case REG_SS_MGMT_SUPPORT:
1336                                 case REG_IP_MGMT_MODE:
1337                                 case REG_IP_VERSION:
1338                                 case REG_UL_TRANSPORT_CIDS_SUPPORTED:
1339                                 case REG_IP_PHS_SDU_ENCAP:
1340                                 case REG_MAX_CLASSIFIERS_SUPPORTED:
1341                                 case REG_PHS_SUPPORT:
1342                                 case REG_ARQ_SUPPORT:
1343                                 case REG_DSX_FLOW_CONTROL:
1344                                 case REG_MAC_CRC_SUPPORT:
1345                                 case REG_MCA_FLOW_CONTROL:
1346                                 case REG_MCAST_POLLING_CIDS:
1347                                 case REG_NUM_DL_TRANS_CID:
1348                                 case REG_MAC_ADDRESS:
1349 #ifdef WIMAX_16E_2005
1350                                 case REG_TLV_T_20_MAX_MAC_DATA_PER_FRAME_SUPPORT:
1351                                 case REG_TLV_T_21_PACKING_SUPPORT:
1352                                 case REG_TLV_T_22_MAC_EXTENDED_RTPS_SUPPORT:
1353                                 case REG_TLV_T_23_MAX_NUM_BURSTS_TRANSMITTED_CONCURRENTLY_TO_THE_MS:
1354                                 case REG_TLV_T_26_METHOD_FOR_ALLOCATING_IP_ADDR_SECONDARY_MGMNT_CONNECTION:
1355                                 case REG_TLV_T_27_HANDOVER_SUPPORTED:
1356                                 case REG_TLV_T_29_HO_PROCESS_OPTIMIZATION_MS_TIMER:
1357                                 case REG_TLV_T_31_MOBILITY_FEATURES_SUPPORTED:
1358                                 case REG_TLV_T_40_ARQ_ACK_TYPE:
1359                                 case REG_TLV_T_41_MS_HO_CONNECTIONS_PARAM_PROCESSING_TIME:
1360                                 case REG_TLV_T_42_MS_HO_TEK_PROCESSING_TIME:
1361                                 case REG_TLV_T_43_MAC_HEADER_AND_EXTENDED_SUBHEADER_SUPPORT:
1362                                 case REG_REQ_BS_SWITCHING_TIMER:
1363                                 case REG_POWER_SAVING_CLASS_CAPABILITY:
1364 #endif
1365                                         /* Decode REG-REQ sub-TLV's. */
1366                                         dissect_extended_tlv(reg_req_tree, tlv_type, tvb, tlv_offset, tlv_len, pinfo, offset, proto_mac_mgmt_msg_reg_req_decoder);
1367                                         break;
1368                                 case REG_REQ_SECONDARY_MGMT_CID:
1369                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_req_secondary_mgmt_cid, tvb, tlv_offset, 2, FALSE);
1370                                         proto_tree_add_item(tlv_tree, hf_reg_req_secondary_mgmt_cid, tvb, tlv_offset, 2, FALSE);
1371                                         break;
1372                                 case REG_REQ_TLV_T_32_SLEEP_MODE_RECOVERY_TIME:
1373                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_req_tlv_t_32_sleep_mode_recovery_time, tvb, tlv_offset, tlv_len, FALSE);
1374                                         proto_tree_add_item(tlv_tree, hf_reg_req_tlv_t_32_sleep_mode_recovery_time, tvb, tlv_offset, 1, FALSE);
1375                                         break;
1376                                 case REG_REQ_TLV_T_33_MS_PREV_IP_ADDR:
1377                                         if ( tlv_len == 4 ) {
1378                                                 tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_ms_previous_ip_address_v4, tvb, tlv_offset, tlv_len, FALSE);
1379                                                 proto_tree_add_item(tlv_tree, hf_ms_previous_ip_address_v4, tvb, tlv_offset, tlv_len, FALSE);
1380                                         } else if ( tlv_len == 16 ) {
1381                                                 tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_ms_previous_ip_address_v6, tvb, tlv_offset, tlv_len, FALSE);
1382                                                 proto_tree_add_item(tlv_tree, hf_ms_previous_ip_address_v6, tvb, tlv_offset, tlv_len, FALSE);
1383                                         }
1384                                         break;
1385                                 case REG_TLV_T_37_IDLE_MODE_TIMEOUT:
1386                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_idle_mode_timeout, tvb, tlv_offset, tlv_len, FALSE);
1387                                         proto_tree_add_item(tlv_tree, hf_idle_mode_timeout, tvb, tlv_offset, tlv_len, FALSE);
1388                                         break;
1389                                 case REG_REQ_TLV_T_45_MS_PERIODIC_RANGING_TIMER_INFO:
1390                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_req_tlv_t_45_ms_periodic_ranging_timer, tvb, tlv_offset, tlv_len, FALSE);
1391                                         proto_tree_add_item(tlv_tree, hf_reg_req_tlv_t_45_ms_periodic_ranging_timer, tvb, tlv_offset, tlv_len, FALSE);
1392                                         break;
1393                                 case REG_HANDOVER_INDICATION_READINESS_TIMER:
1394                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_46_handover_indication_readiness_timer, tvb, tlv_offset, tlv_len, FALSE);
1395                                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_46_handover_indication_readiness_timer, tvb, tlv_offset, tlv_len, FALSE);
1396                                         break;
1397
1398                                 case DSx_UPLINK_FLOW:
1399                                         /* display Uplink Service Flow Encodings info */
1400                                         /* add subtree */
1401                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, tlv_offset, tlv_len, "Uplink Service Flow Encodings (%u byte(s))", tlv_len);
1402                                         /* decode and display the DL Service Flow Encodings */
1403                                         wimax_service_flow_encodings_decoder(tvb_new_subset(tvb, tlv_offset, tlv_len, tlv_len), pinfo, tlv_tree);
1404                                         break;
1405                                 case DSx_DOWNLINK_FLOW:
1406                                         /* display Downlink Service Flow Encodings info */
1407                                         /* add subtree */
1408                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, tlv_offset, tlv_len, "Downlink Service Flow Encodings (%u byte(s))", tlv_len);
1409                                         /* decode and display the DL Service Flow Encodings */
1410                                         wimax_service_flow_encodings_decoder(tvb_new_subset(tvb, tlv_offset, tlv_len, tlv_len), pinfo, tlv_tree);
1411                                         break;
1412                                 case HMAC_TUPLE:        /* Table 348d */
1413                                         /* decode and display the HMAC Tuple */
1414                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, tlv_offset, tlv_len, "HMAC Tuple (%u byte(s))", tlv_len);
1415                                         wimax_hmac_tuple_decoder(tlv_tree, tvb, tlv_offset, tlv_len);
1416                                         hmac_found = TRUE;
1417                                         break;
1418                                 case CMAC_TUPLE:        /* Table 348b */
1419                                         /* decode and display the CMAC Tuple */
1420                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, tlv_offset, tlv_len, "CMAC Tuple (%u byte(s))", tlv_len);
1421                                         wimax_cmac_tuple_decoder(tlv_tree, tvb, tlv_offset, tlv_len);
1422                                         break;
1423                                 default:
1424                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_tlv_type, tvb, tlv_offset, tlv_len, FALSE);
1425                                         proto_tree_add_item(tlv_tree, hf_tlv_type, tvb, tlv_offset, tlv_len, FALSE);
1426                                         break;
1427                         }
1428                         /* update the offset */
1429                         offset = tlv_len + tlv_offset;
1430                 } /* End while() looping through the tvb. */
1431                 if (!hmac_found)
1432                         proto_item_append_text(reg_req_tree, " (HMAC Tuple is missing !)");
1433         }
1434 }