plugins/wimax/msg_reg_req.c

   1 /* msg_reg_req.c
   2  * WiMax MAC Management REG-REQ Message decoder
   3  *
   4  * Copyright (c) 2007 by Intel Corporation.
   5  *
   6  * Author: John R. Underwood <junderx@yahoo.com>
   7  *
   8  * $Id$
   9  *
  10  * Wireshark - Network traffic analyzer
  11  * By Gerald Combs <gerald@wireshark.org>
  12  * Copyright 1999 Gerald Combs
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  27  */
  28
  29 /* Include files */
  30
  31 #ifdef HAVE_CONFIG_H
  32 #include "config.h"
  33 #endif
  34
  35 #define WIMAX_16E_2005
  36
  37 #include "moduleinfo.h"
  38
  39 #include <glib.h>
  40 #include <epan/packet.h>
  41 #include <epan/prefs.h>
  42 #include "crc.h"
  43 #include "wimax_tlv.h"
  44 #include "wimax_mac.h"
  45 #include "wimax_utils.h"
  46
  47 extern gint proto_wimax;
  48 extern gboolean include_cor2_changes;
  49
  50 /* Forward reference */
  51 void dissect_mac_mgmt_msg_reg_req_decoder(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree);
  52
  53
  54 gint proto_mac_mgmt_msg_reg_req_decoder = -1;
  55 static gint ett_mac_mgmt_msg_reg_req_decoder = -1;
  56
  57 /* Setup protocol subtree array */
  58 static gint *ett[] =
  59 {
  60         &ett_mac_mgmt_msg_reg_req_decoder
  61 };
  62
  63 /* REG-REQ fields */
  64 static gint hf_reg_ss_mgmt_support                   = -1;
  65 static gint hf_reg_ip_mgmt_mode                      = -1;
  66 static gint hf_reg_ip_version                        = -1;
  67 static gint hf_reg_req_secondary_mgmt_cid            = -1;
  68 static gint hf_reg_ul_cids                           = -1;
  69 static gint hf_reg_max_classifiers                   = -1;
  70 static gint hf_reg_phs                               = -1;
  71 static gint hf_reg_arq                               = -1;
  72 static gint hf_reg_dsx_flow_control                  = -1;
  73 static gint hf_reg_mac_crc_support                   = -1;
  74 static gint hf_reg_mca_flow_control                  = -1;
  75 static gint hf_reg_mcast_polling_cids                = -1;
  76 static gint hf_reg_num_dl_trans_cid                  = -1;
  77 static gint hf_reg_mac_address                       = -1;
  78 static gint hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame      = -1;
  79 static gint hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame      = -1;
  80 static gint hf_reg_tlv_t_21_packing_support                        = -1;
  81 static gint hf_reg_tlv_t_22_mac_extended_rtps_support              = -1;
  82 static gint hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms = -1;
  83 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp     = -1;
  84 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4 = -1;
  85 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6   = -1;
  86 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6     = -1;
  87 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd     = -1;
  88 static gint hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable          = -1;
  89 static gint hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps = -1;
  90 static gint hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map = -1;
  91 static gint hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps       = -1;
  92 static gint hf_reg_tlv_t_27_handover_mdho_ul_multiple              = -1;
  93 static gint hf_reg_tlv_t_27_handover_reserved                      = -1;
  94 static gint hf_reg_tlv_t_29_ho_process_opt_ms_timer                = -1;
  95 static gint hf_reg_tlv_t_31_mobility_handover                      = -1;
  96 static gint hf_reg_tlv_t_31_mobility_sleep_mode                    = -1;
  97 static gint hf_reg_tlv_t_31_mobility_idle_mode                     = -1;
  98 static gint hf_reg_req_tlv_t_32_sleep_mode_recovery_time           = -1;
  99 static gint hf_ms_previous_ip_address_v4                           = -1;
 100 static gint hf_ms_previous_ip_address_v6                           = -1;
 101 static gint hf_idle_mode_timeout                                   = -1;
 102 static gint hf_reg_req_tlv_t_45_ms_periodic_ranging_timer          = -1;
 103 static gint hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry = -1;
 104 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry = -1;
 105 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry = -1;
 106 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack = -1;
 107 static gint hf_reg_tlv_t_40_arq_ack_type_reserved                  = -1;
 108 static gint hf_reg_tlv_t_41_ho_connections_param_processing_time   = -1;
 109 static gint hf_reg_tlv_t_42_ho_tek_processing_time                 = -1;
 110 static gint hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support = -1;
 111 static gint hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support = -1;
 112 static gint hf_reg_tlv_t_43_cqich_allocation_request_header_support = -1;
 113 static gint hf_reg_tlv_t_43_phy_channel_report_header_support      = -1;
 114 static gint hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support = -1;
 115 static gint hf_reg_tlv_t_43_sn_report_header_support               = -1;
 116 static gint hf_reg_tlv_t_43_feedback_header_support                = -1;
 117 static gint hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter = -1;
 118 static gint hf_reg_tlv_t_43_sdu_sn_parameter                       = -1;
 119 static gint hf_reg_tlv_t_43_dl_sleep_control_extended_subheader    = -1;
 120 static gint hf_reg_tlv_t_43_feedback_request_extended_subheader    = -1;
 121 static gint hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader  = -1;
 122 static gint hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader  = -1;
 123 static gint hf_reg_tlv_t_43_mini_feedback_extended_subheader       = -1;
 124 static gint hf_reg_tlv_t_43_sn_request_extended_subheader          = -1;
 125 static gint hf_reg_tlv_t_43_pdu_sn_short_extended_subheader        = -1;
 126 static gint hf_reg_tlv_t_43_pdu_sn_long_extended_subheader         = -1;
 127 static gint hf_reg_tlv_t_43_reserved                               = -1;
 128 static gint hf_reg_tlv_t_46_handover_indication_readiness_timer    = -1;
 129 static gint hf_reg_req_min_time_for_intra_fa                       = -1;
 130 static gint hf_reg_req_min_time_for_inter_fa                       = -1;
 131 static gint hf_reg_encap_atm_4                                     = -1;
 132 static gint hf_reg_encap_ipv4_4                                      = -1;
 133 static gint hf_reg_encap_ipv6_4                                      = -1;
 134 static gint hf_reg_encap_802_3_4                                     = -1;
 135 static gint hf_reg_encap_802_1q_4                                    = -1;
 136 static gint hf_reg_encap_ipv4_802_3_4                                = -1;
 137 static gint hf_reg_encap_ipv6_802_3_4                                = -1;
 138 static gint hf_reg_encap_ipv4_802_1q_4                               = -1;
 139 static gint hf_reg_encap_ipv6_802_1q_4                               = -1;
 140 static gint hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4  = -1;
 141 static gint hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4 = -1;
 142 static gint hf_reg_encap_packet_ip_rohc_header_compression_4         = -1;
 143 static gint hf_reg_encap_packet_ip_ecrtp_header_compression_4        = -1;
 144 static gint hf_reg_encap_rsvd_4                                     = -1;
 145 static gint hf_reg_encap_atm_2                                     = -1;
 146 static gint hf_reg_encap_ipv4_2                                      = -1;
 147 static gint hf_reg_encap_ipv6_2                                      = -1;
 148 static gint hf_reg_encap_802_3_2                                     = -1;
 149 static gint hf_reg_encap_802_1q_2                                    = -1;
 150 static gint hf_reg_encap_ipv4_802_3_2                                = -1;
 151 static gint hf_reg_encap_ipv6_802_3_2                                = -1;
 152 static gint hf_reg_encap_ipv4_802_1q_2                               = -1;
 153 static gint hf_reg_encap_ipv6_802_1q_2                               = -1;
 154 static gint hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2  = -1;
 155 static gint hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2 = -1;
 156 static gint hf_reg_encap_packet_ip_rohc_header_compression_2         = -1;
 157 static gint hf_reg_encap_packet_ip_ecrtp_header_compression_2        = -1;
 158 static gint hf_reg_encap_rsvd_2                                     = -1;
 159 static gint hf_tlv_type                                            = -1;
 160 static gint hf_reg_invalid_tlv                                     = -1;
 161 static gint hf_reg_power_saving_class_type_i                       = -1;
 162 static gint hf_reg_power_saving_class_type_ii                      = -1;
 163 static gint hf_reg_power_saving_class_type_iii                     = -1;
 164 static gint hf_reg_multi_active_power_saving_classes               = -1;
 165 static gint hf_reg_total_power_saving_class_instances              = -1;
 166 static gint hf_reg_power_saving_class_reserved                     = -1;
 167
 168 static gint hf_reg_req_message_type                                = -1;
 169
 170 /* STRING RESOURCES */
 171
 172 static const true_false_string tfs_reg_ip_mgmt_mode = {
 173     "IP-managed mode",
 174     "Unmanaged mode"
 175 };
 176
 177 static const true_false_string tfs_reg_ss_mgmt_support = {
 178     "secondary management connection",
 179     "no secondary management connection"
 180 };
 181
 182 static const true_false_string tfs_arq_enable = {
 183             "ARQ Requested/Accepted",
 184                 "ARQ Not Requested/Accepted"
 185 };
 186
 187 static const true_false_string tfs_arq_deliver_in_order = {
 188             "Order of delivery is preserved",
 189                 "Order of delivery is not preserved"
 190 };
 191
 192 static const true_false_string tfs_reg_fbss_mdho_ho_disable = {
 193     "Disable",
 194     "Enable"
 195 };
 196
 197 static const value_string vals_reg_ip_version[] = {
 198     {0x1,                               "IPv4"},
 199     {0x2,                               "IPV6"},
 200     {0,                                 NULL}
 201 };
 202
 203 static const value_string vals_reg_phs_support[] = {
 204     {0,                                 "no PHS support"},
 205     {1,                                 "ATM PHS"},
 206     {2,                                 "Packet PHS"},
 207     {3,                                 "ATM and Packet PHS"},
 208     {0,                                 NULL}
 209 };
 210
 211 static const true_false_string tfs_supported = {
 212     "supported",
 213     "unsupported"
 214 };
 215
 216 static const true_false_string tfs_mac_crc_support = {
 217     "MAC CRC Support (Default)",
 218     "No MAC CRC Support"
 219 };
 220
 221 static const value_string tfs_support[] = {
 222     {0,                                 "not supported"},
 223     {1,                                 "supported"},
 224     {0,                                 NULL}
 225 };
 226
 227 /* REG-REQ fields display */
 228 static hf_register_info hf[] =
 229 {
 230         {
 231                 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp,
 232                 {
 233                         "DHCP", "wmx.reg.alloc_sec_mgmt_dhcp",
 234                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, "", HFILL
 235                 }
 236         },
 237         {
 238                 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6,
 239                 {
 240                         "DHCPv6", "wmx.reg.alloc_sec_mgmt_dhcpv6",
 241                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, "", HFILL
 242                 }
 243         },
 244         {
 245                 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6,
 246                 {
 247                         "IPv6 Stateless Address Autoconfiguration", "wmx.reg.alloc_sec_mgmt_ipv6",
 248                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, "", HFILL
 249                 }
 250         },
 251         {
 252                 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4,
 253                 {
 254                         "Mobile IPv4", "wmx.reg.alloc_sec_mgmt_mobile_ipv4",
 255                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, "", HFILL
 256                 }
 257         },
 258         {
 259                 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd,
 260                 {
 261                         "Reserved", "wmx.reg.alloc_sec_mgmt_rsvd",
 262                         FT_UINT8, BASE_DEC, NULL, 0xF0, "", HFILL
 263                 }
 264         },
 265         {
 266                 &hf_reg_arq,
 267                 {
 268                         "ARQ support", "wmx.reg.arq",
 269                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x0, "", HFILL
 270                 }
 271         },
 272         {
 273                 &hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry,
 274                 {
 275                         "Cumulative ACK entry", "wmx.reg.arq_ack_type_cumulative_ack_entry",
 276                         FT_UINT8, BASE_DEC, NULL, 0x2, "", HFILL
 277                 }
 278         },
 279         {
 280                 &hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack,
 281                 {
 282                         "Cumulative ACK with Block Sequence ACK", "wmx.reg.arq_ack_type_cumulative_ack_with_block_sequence_ack",
 283                         FT_UINT8, BASE_DEC, NULL, 0x8, "", HFILL
 284                 }
 285         },
 286         {
 287                 &hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry,
 288                 {
 289                         "Cumulative with Selective ACK entry", "wmx.reg.arq_ack_type_cumulative_with_selective_ack_entry",
 290                         FT_UINT8, BASE_DEC, NULL, 0x4, "", HFILL
 291                 }
 292         },
 293         {
 294                 &hf_reg_tlv_t_40_arq_ack_type_reserved,
 295                 {
 296                         "Reserved", "wmx.reg.arq_ack_type_reserved",
 297                         FT_UINT8, BASE_DEC, NULL, 0xf0, "", HFILL
 298                 }
 299         },
 300         {
 301                 &hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry,
 302                 {
 303                         "Selective ACK entry", "wmx.reg.arq_ack_type_selective_ack_entry",
 304                         FT_UINT8, BASE_DEC, NULL, 0x1, "", HFILL
 305                 }
 306         },
 307         {
 308                 &hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support,
 309                 {
 310                         "Bandwidth request and CINR report header support", "wmx.reg.bandwidth_request_cinr_report_header_support",
 311                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x2, "", HFILL
 312                 }
 313         },
 314         {
 315                 &hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support,
 316                 {
 317                         "Bandwidth request and uplink sleep control header support", "wmx.reg.bandwidth_request_ul_sleep_control_header_support",
 318                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x10, "", HFILL
 319                 }
 320         },
 321         {
 322                 &hf_reg_tlv_t_43_cqich_allocation_request_header_support,
 323                 {
 324                         "CQICH Allocation Request header support", "wmx.reg.cqich_allocation_request_header_support",
 325                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x4, "", HFILL
 326                 }
 327         },
 328         {
 329                 &hf_reg_tlv_t_43_dl_sleep_control_extended_subheader,
 330                 {
 331                         "Downlink sleep control extended subheader", "wmx.reg.dl_sleep_control_extended_subheader",
 332                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x800, "", HFILL
 333                 }
 334         },
 335         {
 336                 &hf_reg_dsx_flow_control,
 337                 {
 338                         "DSx flow control", "wmx.reg.dsx_flow_control",
 339                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 340                 }
 341         },
 342         /* When REG-REQ TLV 7 is length 2 */
 343         {
 344                 &hf_reg_encap_802_1q_2,
 345                 {
 346                         "Packet, 802.1Q VLAN", "wmx.reg.encap_802_1q",
 347                         FT_UINT16, BASE_HEX, NULL, 0x0010, "", HFILL
 348                 }
 349         },
 350         {
 351                 &hf_reg_encap_802_3_2,
 352                 {
 353                         "Packet, 802.3/Ethernet", "wmx.reg.encap_802_3",
 354                         FT_UINT16, BASE_HEX, NULL, 0x00000008, "", HFILL
 355                 }
 356         },
 357         {
 358                 &hf_reg_encap_atm_2,
 359                 {
 360                         "ATM", "wmx.reg.encap_atm",
 361                         FT_UINT16, BASE_HEX, NULL, 0x00000001, "", HFILL
 362                 }
 363         },
 364         {
 365                 &hf_reg_encap_ipv4_2,
 366                 {
 367                         "Packet, IPv4", "wmx.reg.encap_ipv4",
 368                         FT_UINT16, BASE_HEX, NULL, 0x00000002, "", HFILL
 369                 }
 370         },
 371         {
 372                 &hf_reg_encap_ipv6_2,
 373                 {
 374                         "Packet, IPv6", "wmx.reg.encap_ipv6",
 375                         FT_UINT16, BASE_HEX, NULL, 0x00000004, "", HFILL
 376                 }
 377         },
 378         {
 379                 &hf_reg_encap_ipv4_802_1q_2,
 380                 {
 381                         "Packet, IPv4 over 802.1Q VLAN", "wmx.reg.encap_ipv4_802_1q",
 382                         FT_UINT16, BASE_HEX, NULL, 0x00000080, "", HFILL
 383                 }
 384         },
 385         {
 386                 &hf_reg_encap_ipv4_802_3_2,
 387                 {
 388                         "Packet, IPv4 over 802.3/Ethernet", "wmx.reg.encap_ipv4_802_3",
 389                         FT_UINT16, BASE_HEX, NULL, 0x00000020, "", HFILL
 390                 }
 391         },
 392         {
 393                 &hf_reg_encap_ipv6_802_1q_2,
 394                 {
 395                         "Packet, IPv6 over 802.1Q VLAN", "wmx.reg.encap_ipv6_802_1q",
 396                         FT_UINT16, BASE_HEX, NULL, 0x00000100, "", HFILL
 397                 }
 398         },
 399         {
 400                 &hf_reg_encap_ipv6_802_3_2,
 401                 {
 402                         "Packet, IPv6 over 802.3/Ethernet", "wmx.reg.encap_ipv6_802_3",
 403                         FT_UINT16, BASE_HEX, NULL, 0x00000040, "", HFILL
 404                 }
 405         },
 406         {
 407                 &hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2,
 408                 {
 409                         "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ECRTP header compression", "wmx.reg.encap_packet_802_3_ethernet_and_ecrtp_header_compression",
 410                         FT_UINT16, BASE_HEX, NULL, 0x00000400, "", HFILL
 411                 }
 412         },
 413         {
 414                 &hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2,
 415                 {
 416                         "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ROHC header compression", "wmx.reg.encap_packet_802_3_ethernet_and_rohc_header_compression",
 417                         FT_UINT16, BASE_HEX, NULL, 0x00000200, "", HFILL
 418                 }
 419         },
 420         {
 421                 &hf_reg_encap_packet_ip_ecrtp_header_compression_2,
 422                 {
 423                         "Packet, IP (v4 or v6) with ECRTP header compression", "wmx.reg.encap_packet_ip_ecrtp_header_compression",
 424                         FT_UINT16, BASE_HEX, NULL, 0x00001000, "", HFILL
 425                 }
 426         },
 427         {
 428                 &hf_reg_encap_packet_ip_rohc_header_compression_2,
 429                 {
 430                         "Packet, IP (v4 or v6) with ROHC header compression", "wmx.reg.encap_packet_ip_rohc_header_compression",
 431                         FT_UINT16, BASE_HEX, NULL, 0x00000800, "", HFILL
 432                 }
 433         },
 434         {
 435                 &hf_reg_encap_rsvd_2,
 436                 {
 437                         "Reserved", "wmx.reg.encap_rsvd",
 438                         FT_UINT16, BASE_HEX, NULL, 0x0000E000, "", HFILL
 439                 }
 440         },
 441         /* When REG-REQ TLV 7 is length 4 */
 442         {
 443                 &hf_reg_encap_802_1q_4,
 444                 {
 445                         "Packet, 802.1Q VLAN", "wmx.reg.encap_802_1q",
 446                         FT_UINT32, BASE_HEX, NULL, 0x0010, "", HFILL
 447                 }
 448         },
 449         {
 450                 &hf_reg_encap_802_3_4,
 451                 {
 452                         "Packet, 802.3/Ethernet", "wmx.reg.encap_802_3",
 453                         FT_UINT32, BASE_HEX, NULL, 0x00000008, "", HFILL
 454                 }
 455         },
 456         {
 457                 &hf_reg_encap_atm_4,
 458                 {
 459                         "ATM", "wmx.reg.encap_atm",
 460                         FT_UINT32, BASE_HEX, NULL, 0x00000001, "", HFILL
 461                 }
 462         },
 463         {
 464                 &hf_reg_encap_ipv4_4,
 465                 {
 466                         "Packet, IPv4", "wmx.reg.encap_ipv4",
 467                         FT_UINT32, BASE_HEX, NULL, 0x00000002, "", HFILL
 468                 }
 469         },
 470         {
 471                 &hf_reg_encap_ipv4_802_1q_4,
 472                 {
 473                         "Packet, IPv4 over 802.1Q VLAN", "wmx.reg.encap_ipv4_802_1q",
 474                         FT_UINT32, BASE_HEX, NULL, 0x00000080, "", HFILL
 475                 }
 476         },
 477         {
 478                 &hf_reg_encap_ipv4_802_3_4,
 479                 {
 480                         "Packet, IPv4 over 802.3/Ethernet", "wmx.reg.encap_ipv4_802_3",
 481                         FT_UINT32, BASE_HEX, NULL, 0x00000020, "", HFILL
 482                 }
 483         },
 484         {
 485                 &hf_reg_encap_ipv6_4,
 486                 {
 487                         "Packet, IPv6", "wmx.reg.encap_ipv6",
 488                         FT_UINT32, BASE_HEX, NULL, 0x00000004, "", HFILL
 489                 }
 490         },
 491         {
 492                 &hf_reg_encap_ipv6_802_1q_4,
 493                 {
 494                         "Packet, IPv6 over 802.1Q VLAN", "wmx.reg.encap_ipv6_802_1q",
 495                         FT_UINT32, BASE_HEX, NULL, 0x00000100, "", HFILL
 496                 }
 497         },
 498         {
 499                 &hf_reg_encap_ipv6_802_3_4,
 500                 {
 501                         "Packet, IPv6 over 802.3/Ethernet", "wmx.reg.encap_ipv6_802_3",
 502                         FT_UINT32, BASE_HEX, NULL, 0x00000040, "", HFILL
 503                 }
 504         },
 505         {
 506                 &hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4,
 507                 {
 508                         "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ECRTP header compression", "wmx.reg.encap_packet_802_3_ethernet_and_ecrtp_header_compression",
 509                         FT_UINT32, BASE_HEX, NULL, 0x00000400, "", HFILL
 510                 }
 511         },
 512         {
 513                 &hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4,
 514                 {
 515                         "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ROHC header compression", "wmx.reg.encap_packet_802_3_ethernet_and_rohc_header_compression",
 516                         FT_UINT32, BASE_HEX, NULL, 0x00000200, "", HFILL
 517                 }
 518         },
 519         {
 520                 &hf_reg_encap_packet_ip_ecrtp_header_compression_4,
 521                 {
 522                         "Packet, IP (v4 or v6) with ECRTP header compression", "wmx.reg.encap_packet_ip_ecrtp_header_compression",
 523                         FT_UINT32, BASE_HEX, NULL, 0x00001000, "", HFILL
 524                 }
 525         },
 526         {
 527                 &hf_reg_encap_packet_ip_rohc_header_compression_4,
 528                 {
 529                         "Packet, IP (v4 or v6) with ROHC header compression", "wmx.reg.encap_packet_ip_rohc_header_compression",
 530                         FT_UINT32, BASE_HEX, NULL, 0x00000800, "", HFILL
 531                 }
 532         },
 533         {
 534                 &hf_reg_encap_rsvd_4,
 535                 {
 536                         "Reserved", "wmx.reg.encap_rsvd",
 537                         FT_UINT32, BASE_HEX, NULL, 0xFFFFE000, "", HFILL
 538                 }
 539         },
 540         {
 541                 &hf_reg_tlv_t_22_mac_extended_rtps_support,
 542                 {
 543                         "MAC extended rtPS support", "wmx.reg.ext_rtps_support",
 544                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, "", HFILL
 545                 }
 546         },
 547         {
 548                 &hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps,
 549                 {
 550                         "FBSS/MDHO DL RF Combining with monitoring MAPs from active BSs", "wmx.reg.fbss_mdho_dl_rf_combining",
 551                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, "", HFILL
 552                 }
 553         },
 554         {
 555                 &hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support,
 556                 {
 557                         "Bandwidth request and UL Tx Power Report header support",
 558                         "wimax.reg.bandwidth_request_ul_tx_pwr_report_header_support",
 559                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x1, "", HFILL
 560                 }
 561         },
 562         {
 563                 &hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable,
 564                 {
 565                         "MDHO/FBSS HO. BS ignore all other bits when set to 1", "wmx.reg.fbss_mdho_ho_disable",
 566                         FT_BOOLEAN, 8, TFS(&tfs_reg_fbss_mdho_ho_disable), 0x01, "", HFILL
 567                 }
 568         },
 569         {
 570                 &hf_reg_tlv_t_43_feedback_header_support,
 571                 {
 572                         "Feedback header support", "wmx.reg.feedback_header_support",
 573                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x40, "", HFILL
 574                 }
 575         },
 576         {
 577                 &hf_reg_tlv_t_43_feedback_request_extended_subheader,
 578                 {
 579                         "Feedback request extended subheader", "wmx.reg.feedback_request_extended_subheader",
 580                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x1000, "", HFILL
 581                 }
 582         },
 583         {
 584                 &hf_reg_tlv_t_46_handover_indication_readiness_timer,
 585                 {
 586                         "Handover indication readiness timer", "wmx.reg.handover_indication_readiness_timer",
 587                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 588                 }
 589         },
 590         {
 591                 &hf_reg_tlv_t_27_handover_reserved,
 592                 {
 593                         "Reserved", "wmx.reg.handover_reserved",
 594                         FT_UINT8, BASE_DEC, NULL, 0xE0, "", HFILL
 595                 }
 596         },
 597         {
 598                 &hf_reg_tlv_t_41_ho_connections_param_processing_time,
 599                 {
 600                         "MS HO connections parameters processing time", "wmx.reg.ho_connections_param_processing_time",
 601                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 602                 }
 603         },
 604         {
 605                 &hf_reg_tlv_t_29_ho_process_opt_ms_timer,
 606                 {
 607                         "HO Process Optimization MS Timer", "wmx.reg.ho_process_opt_ms_timer",
 608                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 609                 }
 610         },
 611         {
 612                 &hf_reg_tlv_t_42_ho_tek_processing_time,
 613                 {
 614                         "MS HO TEK processing time", "wmx.reg.ho_tek_processing_time",
 615                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 616                 }
 617         },
 618         {
 619                 &hf_idle_mode_timeout,
 620                 {
 621                         "Idle Mode Timeout", "wmx.reg.idle_mode_timeout",
 622                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 623                 }
 624         },
 625         {
 626                 &hf_reg_ip_mgmt_mode,
 627                 {
 628                         "IP management mode", "wmx.reg.ip_mgmt_mode",
 629                         FT_BOOLEAN, 8, TFS(&tfs_reg_ip_mgmt_mode), 0x0, "", HFILL
 630                 }
 631         },
 632         {
 633                 &hf_reg_ip_version,
 634                 {
 635                         "IP version", "wmx.reg.ip_version",
 636                         FT_UINT8, BASE_HEX, VALS(vals_reg_ip_version), 0x0, "", HFILL
 637                 }
 638         },
 639         {
 640                 &hf_reg_mac_address,
 641                 {
 642                         "MAC Address of the SS", "wmx.reg.mac_address",
 643                         FT_ETHER, BASE_DEC, NULL, 0x0, "", HFILL
 644                 }
 645         },
 646         {
 647                 &hf_reg_mac_crc_support,
 648                 {
 649                         "MAC CRC", "wmx.reg.mac_crc_support",
 650                         FT_BOOLEAN, 8, TFS(&tfs_mac_crc_support), 0x0, "", HFILL
 651                 }
 652         },
 653         {
 654                 &hf_reg_max_classifiers,
 655                 {
 656                         "Maximum number of classification rules", "wmx.reg.max_classifiers",
 657                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 658                 }
 659         },
 660         {
 661                 &hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms,
 662                 {
 663                         "Maximum number of bursts transmitted concurrently to the MS", "wmx.reg.max_num_bursts_to_ms",
 664                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 665                 }
 666         },
 667         {
 668                 &hf_reg_mca_flow_control,
 669                 {
 670                         "MCA flow control", "wmx.reg.mca_flow_control",
 671                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 672                 }
 673         },
 674         {
 675                 &hf_reg_mcast_polling_cids,
 676                 {
 677                         "Multicast polling group CID support", "wmx.reg.mcast_polling_cids",
 678                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 679                 }
 680         },
 681         {
 682                 &hf_reg_tlv_t_27_handover_mdho_ul_multiple,
 683                 {
 684                         "MDHO UL Multiple transmission", "wmx.reg.mdh_ul_multiple",
 685                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x10, "", HFILL
 686                 }
 687         },
 688         {
 689                 &hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps,
 690                 {
 691                         "MDHO DL soft combining with monitoring MAPs from active BSs", "wmx.reg.mdho_dl_monitor_maps",
 692                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, "", HFILL
 693                 }
 694         },
 695         {
 696                 &hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map,
 697                 {
 698                         "MDHO DL soft Combining with monitoring single MAP from anchor BS", "wmx.reg.mdho_dl_monitor_single_map",
 699                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, "", HFILL
 700                 }
 701         },
 702         {
 703                 &hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader,
 704                 {
 705                         "MIMO mode feedback request extended subheader", "wmx.reg.mimo_mode_feedback_request_extended_subheader",
 706                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x2000, "", HFILL
 707                 }
 708         },
 709         {
 710                 &hf_reg_tlv_t_43_mini_feedback_extended_subheader,
 711                 {
 712                         "Mini-feedback extended subheader", "wmx.reg.mini_feedback_extended_subheader",
 713                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x8000, "", HFILL
 714                 }
 715         },
 716         {
 717                 &hf_reg_tlv_t_31_mobility_handover,
 718                 {
 719                         "Mobility (handover)", "wmx.reg.mobility_handover",
 720                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, "", HFILL
 721                 }
 722         },
 723         {
 724                 &hf_reg_tlv_t_31_mobility_idle_mode,
 725                 {
 726                         "Idle mode", "wmx.reg.mobility_idle_mode",
 727                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, "", HFILL
 728                 }
 729         },
 730         {
 731                 &hf_reg_tlv_t_31_mobility_sleep_mode,
 732                 {
 733                         "Sleep mode", "wmx.reg.mobility_sleep_mode",
 734                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, "", HFILL
 735                 }
 736         },
 737         {
 738                 &hf_reg_num_dl_trans_cid,
 739                 {
 740                         "Number of Downlink transport CIDs the SS can support", "wmx.reg.dl_cids_supported",
 741                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 742                 }
 743         },
 744         {
 745                 &hf_reg_tlv_t_21_packing_support,
 746                 {
 747                         "Packing support", "wmx.reg.packing.support",
 748                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, "", HFILL
 749                 }
 750         },
 751         {
 752                 &hf_reg_tlv_t_43_pdu_sn_long_extended_subheader,
 753                 {
 754                         "PDU SN (long) extended subheader", "wmx.reg.pdu_sn_long_extended_subheader",
 755                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x40000, "", HFILL
 756                 }
 757         },
 758         {
 759                 &hf_reg_tlv_t_43_pdu_sn_short_extended_subheader,
 760                 {
 761                         "PDU SN (short) extended subheader", "wmx.reg.pdu_sn_short_extended_subheader",
 762                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x20000, "", HFILL
 763                 }
 764         },
 765         {
 766                 &hf_reg_phs,
 767                 {
 768                         "PHS support", "wmx.reg.phs",
 769                         FT_UINT8, BASE_DEC, VALS(vals_reg_phs_support), 0x0, "", HFILL
 770                 }
 771         },
 772         {
 773                 &hf_reg_tlv_t_43_phy_channel_report_header_support,
 774                 {
 775                         "PHY channel report header support", "wmx.reg.phy_channel_report_header_support",
 776                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x8, "", HFILL
 777                 }
 778         },
 779         {
 780                 &hf_reg_tlv_t_43_reserved,
 781                 {
 782                         "Reserved", "wmx.reg.reserved",
 783                         FT_UINT24, BASE_DEC, NULL, 0xf80000, "", HFILL
 784                 }
 785         },
 786         {
 787                 &hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter,
 788                 {
 789                         "SDU_SN extended subheader support", "wmx.reg.sdu_sn_extended_subheader_support",
 790                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x80, "", HFILL
 791                 }
 792         },
 793         {
 794                 &hf_reg_tlv_t_43_sdu_sn_parameter,
 795                 {
 796                         "SDU_SN parameter", "wmx.reg.sdu_sn_parameter",
 797                         FT_UINT24, BASE_DEC, NULL, 0x700, "", HFILL
 798                 }
 799         },
 800         {
 801                 &hf_reg_tlv_t_43_sn_report_header_support,
 802                 {
 803                         "SN report header support", "wmx.reg.sn_report_header_support",
 804                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x20, "", HFILL
 805                 }
 806         },
 807         {
 808                 &hf_reg_tlv_t_43_sn_request_extended_subheader,
 809                 {
 810                         "SN request extended subheader", "wmx.reg.sn_request_extended_subheader",
 811                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x10000, "", HFILL
 812                 }
 813         },
 814         {
 815                 &hf_reg_ss_mgmt_support,
 816                 {
 817                         "SS management support", "wmx.reg.ss_mgmt_support",
 818                         FT_BOOLEAN, 8, TFS(&tfs_reg_ss_mgmt_support), 0x0, "", HFILL
 819                 }
 820         },
 821         {
 822                 &hf_reg_ul_cids,
 823                 {
 824                         "Number of Uplink transport CIDs the SS can support", "wmx.reg.ul_cids_supported",
 825                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 826                 }
 827         },
 828         {
 829                 &hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader,
 830                 {
 831                         "UL Tx power report extended subheader", "wmx.reg.ul_tx_power_report_extended_subheader",
 832                         FT_UINT24, BASE_DEC, VALS(tfs_support), 0x4000, "", HFILL
 833                 }
 834         },
 835         {
 836                 &hf_tlv_type,
 837                 {
 838                         "Unknown TLV Type", "wmx.reg.unknown_tlv_type",
 839                         FT_BYTES, BASE_NONE, NULL, 0x00, "", HFILL
 840                 }
 841         },
 842         {
 843                 &hf_reg_req_message_type,
 844                 {
 845                         "MAC Management Message Type", "wmx.macmgtmsgtype.reg_req",
 846                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 847                 }
 848         },
 849         {
 850                 &hf_reg_invalid_tlv,
 851                 {
 852                         "Invalid TLV", "wmx.reg_req.invalid_tlv",
 853                         FT_BYTES, BASE_HEX, NULL, 0, "", HFILL
 854                 }
 855         },
 856         {
 857                 &hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame,
 858                 {
 859                         "Maximum MAC level DL data per frame", "wmx.reg_req.max_mac_dl_data",
 860                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 861                 }
 862         },
 863         {
 864                 &hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame,
 865                 {
 866                         "Maximum MAC level UL data per frame", "wmx.reg_req.max_mac_ul_data",
 867                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 868                 }
 869         },
 870         {
 871                 &hf_reg_req_min_time_for_inter_fa,
 872                 {
 873                         "Minimum time for inter-FA HO, default=3", "wmx.reg_req.min_time_for_inter_fa",
 874                         FT_UINT8, BASE_HEX, NULL, 0xF0, "", HFILL
 875                 }
 876         },
 877         {
 878                 &hf_reg_req_min_time_for_intra_fa,
 879                 {
 880                         "Minimum time for intra-FA HO, default=2", "wmx.reg_req.min_time_for_intra_fa",
 881                         FT_UINT8, BASE_HEX, NULL, 0x0F, "", HFILL
 882                 }
 883         },
 884         {
 885                 &hf_reg_req_tlv_t_45_ms_periodic_ranging_timer,
 886                 {
 887                         "MS periodic ranging timer information", "wmx.reg_req.ms_periodic_ranging_timer_info",
 888                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 889                 }
 890         },
 891         {       /* IPv4 Mask */
 892                 &hf_ms_previous_ip_address_v4,
 893                 {
 894                         "MS Previous IP address", "wmx.reg_req.ms_prev_ip_addr_v4",
 895                         FT_IPv4, BASE_NONE, NULL, 0x0, "", HFILL
 896                 }
 897         },
 898         {       /* IPv6 Source Address */
 899                 &hf_ms_previous_ip_address_v6,
 900                 {
 901                         "MS Previous IP address", "wmx.reg_req.ms_prev_ip_addr_v6",
 902                         FT_IPv6, BASE_NONE, NULL, 0x0, "", HFILL
 903                 }
 904         },
 905         {
 906                 &hf_reg_req_secondary_mgmt_cid,
 907                 {
 908                         "Secondary Management CID", "wmx.reg_req.secondary_mgmt_cid",
 909                         FT_UINT16, BASE_DEC, NULL, 0x0, "", HFILL
 910                 }
 911         },
 912         {
 913                 &hf_reg_req_tlv_t_32_sleep_mode_recovery_time,
 914                 {
 915                         "Frames required for the MS to switch from sleep to awake-mode", "wmx.reg_req.sleep_recovery",
 916                         FT_UINT8, BASE_DEC, NULL, 0x0, "", HFILL
 917                 }
 918         },
 919         {
 920                 &hf_reg_power_saving_class_type_i,
 921                 {
 922                         "Power saving class type I supported", "wmx.reg.power_saving_class_type_i",
 923                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, "", HFILL
 924                 }
 925         },
 926         {
 927                 &hf_reg_power_saving_class_type_ii,
 928                 {
 929                         "Power saving class type II supported", "wmx.reg.power_saving_class_type_ii",
 930                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, "", HFILL
 931                 }
 932         },
 933         {
 934                 &hf_reg_power_saving_class_type_iii,
 935                 {
 936                         "Power saving class type III supported", "wmx.reg.power_saving_class_type_iii",
 937                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, "", HFILL
 938                 }
 939         },
 940         {
 941                 &hf_reg_multi_active_power_saving_classes,
 942                 {
 943                         "Multiple active power saving classes supported", "wmx.reg.multi_active_power_saving_classes",
 944                         FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, "", HFILL
 945                 }
 946         },
 947         {
 948                 &hf_reg_total_power_saving_class_instances,
 949                 {
 950                         "Total number of power saving class instances of all", "wmx.reg_req.total_power_saving_class_instances",
 951                         FT_UINT16, BASE_DEC, NULL, 0x1F0, "", HFILL
 952                 }
 953         },
 954         {
 955                 &hf_reg_power_saving_class_reserved,
 956                 {
 957                         "Reserved", "wmx.reg.reserved",
 958                         FT_UINT16, BASE_DEC, NULL, 0xFE00, "", HFILL
 959                 }
 960         }
 961 };
 962
 963 /* Decode REG-REQ sub-TLV's. */
 964 void dissect_extended_tlv(proto_tree *reg_req_tree, gint tlv_type, tvbuff_t *tvb, guint tlv_offset, guint tlv_len, packet_info *pinfo, guint offset, gint proto_registry)
 965 {
 966         proto_item *tlv_item = NULL;
 967         proto_tree *tlv_tree = NULL;
 968         proto_tree *sub_tree = NULL;
 969         guint tvb_len;
 970         tlv_info_t tlv_info;
 971         guint tlv_end;
 972         guint length;
 973         guint nblocks;
 974
 975         /* Get the tvb reported length */
 976         tvb_len =  tvb_reported_length(tvb);
 977
 978         /* get the TLV information */
 979         init_tlv_info(&tlv_info, tvb, offset);
 980
 981 #ifdef WIMAX_16E_2005
 982         switch (tlv_type) {
 983                 case REG_ARQ_PARAMETERS:
 984                         /* display ARQ Service Flow Encodings info */
 985                         /* add subtree */
 986                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "ARQ Service Flow Encodings (%u byte(s))", tlv_len);
 987                         /* decode and display the DL Service Flow Encodings */
 988                         wimax_service_flow_encodings_decoder(tvb_new_subset(tvb, tlv_offset, tlv_len, tlv_len), pinfo, tlv_tree);
 989                         break;
 990                 case REG_SS_MGMT_SUPPORT:
 991                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_ss_mgmt_support, tvb, tlv_offset, tlv_len, FALSE);
 992                         proto_tree_add_item(tlv_tree, hf_reg_ss_mgmt_support, tvb, tlv_offset, 1, FALSE);
 993                         break;
 994                 case REG_IP_MGMT_MODE:
 995                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_ip_mgmt_mode, tvb, tlv_offset, tlv_len, FALSE);
 996                         proto_tree_add_item(tlv_tree, hf_reg_ip_mgmt_mode, tvb, tlv_offset, 1, FALSE);
 997                         break;
 998                 case REG_IP_VERSION:
 999                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_ip_version, tvb, tlv_offset, tlv_len, FALSE);
1000                         proto_tree_add_item(tlv_tree, hf_reg_ip_version, tvb, tlv_offset, 1, FALSE);
1001                         break;
1002                 case REG_UL_TRANSPORT_CIDS_SUPPORTED:
1003                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_ul_cids, tvb, tlv_offset, tlv_len, FALSE);
1004                         proto_tree_add_item(tlv_tree, hf_reg_ul_cids, tvb, tlv_offset, tlv_len, FALSE);
1005                         break;
1006
1007                 case REG_POWER_SAVING_CLASS_CAPABILITY:
1008                         /* add TLV subtree */
1009                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Power saving class capability (%d)", tvb_get_ntohs(tvb, tlv_offset));
1010                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_i, tvb, tlv_offset, 2, FALSE);
1011                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_ii, tvb, tlv_offset, 2, FALSE);
1012                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_iii, tvb, tlv_offset, 2, FALSE);
1013                         proto_tree_add_item(tlv_tree, hf_reg_multi_active_power_saving_classes, tvb, tlv_offset, 2, FALSE);
1014                         proto_tree_add_item(tlv_tree, hf_reg_total_power_saving_class_instances, tvb, tlv_offset, 2, FALSE);
1015                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_reserved, tvb, tlv_offset, 2, FALSE);
1016                         break;
1017                 case REG_IP_PHS_SDU_ENCAP:
1018                         /* add TLV subtree */
1019                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Classification/PHS options and SDU encapsulation support 0x%04x", tvb_get_ntohs(tvb, tlv_offset));
1020
1021 #ifdef WIMAX_16E_2005
1022                         if (tlv_len == 2){
1023                                 proto_tree_add_item(tlv_tree, hf_reg_encap_atm_2, tvb, tlv_offset, tlv_len, FALSE);
1024                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_2, tvb, tlv_offset, tlv_len, FALSE);
1025                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_2, tvb, tlv_offset, tlv_len, FALSE);
1026                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_3_2, tvb, tlv_offset, tlv_len, FALSE);
1027                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_1q_2, tvb, tlv_offset, tlv_len, FALSE);
1028                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_3_2, tvb, tlv_offset, tlv_len, FALSE);
1029                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_3_2, tvb, tlv_offset, tlv_len, FALSE);
1030                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_1q_2, tvb, tlv_offset, tlv_len, FALSE);
1031                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_1q_2, tvb, tlv_offset, tlv_len, FALSE);
1032                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2, tvb, tlv_offset, tlv_len, FALSE);
1033                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2, tvb, tlv_offset, tlv_len, FALSE);
1034                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_rohc_header_compression_2, tvb, tlv_offset, tlv_len, FALSE);
1035                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_ecrtp_header_compression_2, tvb, tlv_offset, tlv_len, FALSE);
1036                                 proto_tree_add_item(tlv_tree, hf_reg_encap_rsvd_2, tvb, tlv_offset, tlv_len, FALSE);
1037                         } else if(tlv_len == 4){
1038                                 proto_tree_add_item(tlv_tree, hf_reg_encap_atm_4, tvb, tlv_offset, tlv_len, FALSE);
1039                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_4, tvb, tlv_offset, tlv_len, FALSE);
1040                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_4, tvb, tlv_offset, tlv_len, FALSE);
1041                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_3_4, tvb, tlv_offset, tlv_len, FALSE);
1042                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_1q_4, tvb, tlv_offset, tlv_len, FALSE);
1043                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_3_4, tvb, tlv_offset, tlv_len, FALSE);
1044                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_3_4, tvb, tlv_offset, tlv_len, FALSE);
1045                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_1q_4, tvb, tlv_offset, tlv_len, FALSE);
1046                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_1q_4, tvb, tlv_offset, tlv_len, FALSE);
1047                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4, tvb, tlv_offset, tlv_len, FALSE);
1048                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4, tvb, tlv_offset, tlv_len, FALSE);
1049                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_rohc_header_compression_4, tvb, tlv_offset, tlv_len, FALSE);
1050                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_ecrtp_header_compression_4, tvb, tlv_offset, tlv_len, FALSE);
1051                                 proto_tree_add_item(tlv_tree, hf_reg_encap_rsvd_4, tvb, tlv_offset, tlv_len, FALSE);
1052                         }
1053 #endif
1054                         break;
1055                 case REG_MAX_CLASSIFIERS_SUPPORTED:
1056                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_max_classifiers, tvb, tlv_offset, tlv_len, FALSE);
1057                         proto_tree_add_item(tlv_tree, hf_reg_max_classifiers, tvb, tlv_offset, 2, FALSE);
1058                         break;
1059                 case REG_PHS_SUPPORT:
1060                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_phs, tvb, tlv_offset, tlv_len, FALSE);
1061                         proto_tree_add_item(tlv_tree, hf_reg_phs, tvb, tlv_offset, 1, FALSE);
1062                         break;
1063                 case REG_ARQ_SUPPORT:
1064                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_arq, tvb, tlv_offset, tlv_len, FALSE);
1065                         proto_tree_add_item(tlv_tree, hf_reg_arq, tvb, tlv_offset, 1, FALSE);
1066                         break;
1067                 case REG_DSX_FLOW_CONTROL:
1068                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_dsx_flow_control, tvb, tlv_offset, tlv_len, FALSE);
1069                         tlv_item = proto_tree_add_item(tlv_tree, hf_reg_dsx_flow_control, tvb, tlv_offset, 1, FALSE);
1070                         if (tvb_get_guint8(tvb, tlv_offset) == 0) {
1071                                 proto_item_append_text(tlv_item, " (no limit)");
1072                         }
1073                         break;
1074                 case REG_MAC_CRC_SUPPORT:
1075                         if (!include_cor2_changes) {
1076                                 proto_tree_add_item(reg_req_tree, hf_reg_mac_crc_support, tvb, tlv_offset, 1, FALSE);
1077                                 tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_mac_crc_support, tvb, tlv_offset, tlv_len, FALSE);
1078                                 proto_tree_add_item(tlv_tree, hf_reg_mac_crc_support, tvb, tlv_offset, 1, FALSE);
1079                         } else {
1080                                 /* Unknown TLV Type */
1081                                 tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, (tvb_len - tlv_offset), FALSE);
1082                                 proto_tree_add_item(tlv_tree, hf_tlv_type, tvb, tlv_offset, (tvb_len - tlv_offset), FALSE);
1083                         }
1084                         break;
1085                 case REG_MCA_FLOW_CONTROL:
1086                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_mca_flow_control, tvb, tlv_offset, tlv_len, FALSE);
1087                         tlv_item = proto_tree_add_item(tlv_tree, hf_reg_mca_flow_control, tvb, tlv_offset, 1, FALSE);
1088                         if (tvb_get_guint8(tvb, tlv_offset) == 0) {
1089                                 proto_item_append_text(tlv_item, " (no limit)");
1090                         }
1091                         break;
1092                 case REG_MCAST_POLLING_CIDS:
1093                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_mcast_polling_cids, tvb, tlv_offset, tlv_len, FALSE);
1094                         proto_tree_add_item(tlv_tree, hf_reg_mcast_polling_cids, tvb, tlv_offset, 1, FALSE);
1095                         break;
1096                 case REG_NUM_DL_TRANS_CID:
1097                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_num_dl_trans_cid, tvb, tlv_offset, tlv_len, FALSE);
1098                         proto_tree_add_item(tlv_tree, hf_reg_num_dl_trans_cid, tvb, tlv_offset, 2, FALSE);
1099                         break;
1100                 case REG_MAC_ADDRESS:
1101                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_mac_address, tvb, tlv_offset, tlv_len, FALSE);
1102                         proto_tree_add_item(tlv_tree, hf_reg_mac_address, tvb, tlv_offset, 6, FALSE);
1103                         break;
1104                 case REG_TLV_T_20_MAX_MAC_DATA_PER_FRAME_SUPPORT:
1105                         /* display Maximum MAC level data per frame info */
1106                         /* add subtree */
1107                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Maximum MAC level data per frame (%u byte(s))", tlv_len);
1108                         /* decode and display Maximum MAC level data per frame for UL & DL */
1109                         /* Set endpoint of the subTLVs (tlv_offset + length) */
1110                         tlv_end = tlv_offset + tlv_len;
1111                         /* process subTLVs */
1112                         while ( tlv_offset < tlv_end )
1113                         {       /* get the TLV information */
1114                                 init_tlv_info(&tlv_info, tvb, tlv_offset);
1115                                 /* get the TLV type */
1116                                 tlv_type = get_tlv_type(&tlv_info);
1117                                 /* get the TLV length */
1118                                 length = get_tlv_length(&tlv_info);
1119                                 if(tlv_type == -1 || length > MAX_TLV_LEN || length < 1)
1120                                 {       /* invalid tlv info */
1121                                         if (pinfo->cinfo)
1122                                         {
1123                                                 col_append_sep_str(pinfo->cinfo, COL_INFO, NULL, "REG-REQ TLV error");
1124                                         }
1125                                         proto_tree_add_item(reg_req_tree, hf_reg_invalid_tlv, tvb, offset, (tvb_len - offset), FALSE);
1126                                         break;
1127                                 }
1128                                 /* update the offset */
1129                                 tlv_offset += get_tlv_value_offset(&tlv_info);
1130                                 nblocks = tvb_get_ntohs(tvb, tlv_offset);
1131                                 switch (tlv_type)
1132                                 {
1133                                         case REG_TLV_T_20_1_MAX_MAC_LEVEL_DATA_PER_DL_FRAME:
1134                                                 sub_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, tlv_tree, hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame, tvb, tlv_offset, length, FALSE);
1135                                                 tlv_item = proto_tree_add_item(sub_tree, hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame, tvb, tlv_offset, 2, FALSE);
1136                                                 if ( nblocks == 0 )
1137                                                 {
1138                                                         proto_item_append_text(tlv_item, " (Unlimited bytes)");
1139                                                 } else {
1140                                                         proto_item_append_text(tlv_item, " (%d bytes)", 256 * nblocks);
1141                                                 }
1142                                                 break;
1143                                         case REG_TLV_T_20_2_MAX_MAC_LEVEL_DATA_PER_UL_FRAME:
1144                                                 sub_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, tlv_tree, hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame, tvb, tlv_offset, length, FALSE);
1145                                                 tlv_item = proto_tree_add_item(sub_tree, hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame, tvb, tlv_offset, 2, FALSE);
1146                                                 if ( nblocks == 0 )
1147                                                 {
1148                                                         proto_item_append_text(tlv_item, " (Unlimited bytes)");
1149                                                 } else {
1150                                                         proto_item_append_text(tlv_item, " (%d bytes)", 256 * nblocks);
1151                                                 }
1152                                                 break;
1153                                         default:
1154                                                 sub_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, tlv_tree, hf_reg_invalid_tlv, tvb, tlv_offset, (tlv_end - tlv_offset), FALSE);
1155                                                 proto_tree_add_item(sub_tree, hf_reg_invalid_tlv, tvb, tlv_offset, (tlv_end - tlv_offset), FALSE);
1156                                                 break;
1157                                 }
1158                                 tlv_offset += length;
1159                         }
1160                         break;
1161
1162                 case REG_TLV_T_21_PACKING_SUPPORT:
1163                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_21_packing_support, tvb, tlv_offset, tlv_len, FALSE);
1164                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_21_packing_support, tvb, tlv_offset, 1, FALSE);
1165                         break;
1166                 case REG_TLV_T_22_MAC_EXTENDED_RTPS_SUPPORT:
1167                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_22_mac_extended_rtps_support, tvb, tlv_offset, tlv_len, FALSE);
1168                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_22_mac_extended_rtps_support, tvb, tlv_offset, 1, FALSE);
1169                         break;
1170                 case REG_TLV_T_23_MAX_NUM_BURSTS_TRANSMITTED_CONCURRENTLY_TO_THE_MS:
1171                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms, tvb, tlv_offset, tlv_len, FALSE);
1172                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms, tvb, tlv_offset, 1, FALSE);
1173                         break;
1174                 case REG_TLV_T_26_METHOD_FOR_ALLOCATING_IP_ADDR_SECONDARY_MGMNT_CONNECTION:
1175                         /* add TLV subtree */
1176                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Method for allocating IP address for the secondary management connection (%d)", tvb_get_guint8(tvb, tlv_offset));
1177                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp, tvb, tlv_offset, 1, FALSE);
1178                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4, tvb, tlv_offset, 1, FALSE);
1179                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6, tvb, tlv_offset, 1, FALSE);
1180                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6, tvb, tlv_offset, 1, FALSE);
1181                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd, tvb, tlv_offset, 1, FALSE);
1182                         break;
1183                 case REG_TLV_T_27_HANDOVER_SUPPORTED:
1184                         /* add TLV subtree */
1185                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Handover Support (%d)", tvb_get_guint8(tvb, tlv_offset));
1186                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable, tvb, tlv_offset, 1, FALSE);
1187                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps, tvb, tlv_offset, 1, FALSE);
1188                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map, tvb, tlv_offset, 1, FALSE);
1189                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps, tvb, tlv_offset, 1, FALSE);
1190                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_ul_multiple, tvb, tlv_offset, 1, FALSE);
1191                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_reserved, tvb, tlv_offset, 1, FALSE);
1192                         break;
1193                 case REG_TLV_T_29_HO_PROCESS_OPTIMIZATION_MS_TIMER:
1194                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_29_ho_process_opt_ms_timer, tvb, tlv_offset, tlv_len, FALSE);
1195                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_29_ho_process_opt_ms_timer, tvb, tlv_offset, 1, FALSE);
1196                         break;
1197                 case REG_TLV_T_31_MOBILITY_FEATURES_SUPPORTED:
1198                         /* add TLV subtree */
1199                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Mobility Features Supported (%d)", tvb_get_guint8(tvb, tlv_offset));
1200                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_handover, tvb, tlv_offset, 1, FALSE);
1201                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_sleep_mode, tvb, tlv_offset, 1, FALSE);
1202                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_idle_mode, tvb, tlv_offset, 1, FALSE);
1203                         break;
1204                 case REG_TLV_T_40_ARQ_ACK_TYPE:
1205                         /* add TLV subtree */
1206                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "ARQ ACK Type 0x%02x", tvb_get_guint8(tvb, tlv_offset));
1207                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry, tvb, tlv_offset, 1, FALSE);
1208                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry, tvb, tlv_offset, 1, FALSE);
1209                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry, tvb, tlv_offset, 1, FALSE);
1210                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack, tvb, tlv_offset, 1, FALSE);
1211                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_reserved, tvb, tlv_offset, 1, FALSE);
1212                         break;
1213                 case REG_TLV_T_41_MS_HO_CONNECTIONS_PARAM_PROCESSING_TIME:
1214                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_41_ho_connections_param_processing_time, tvb, tlv_offset, tlv_len, FALSE);
1215                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_41_ho_connections_param_processing_time, tvb, tlv_offset, 1, FALSE);
1216                         break;
1217                 case REG_TLV_T_42_MS_HO_TEK_PROCESSING_TIME:
1218                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_42_ho_tek_processing_time, tvb, tlv_offset, tlv_len, FALSE);
1219                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_42_ho_tek_processing_time, tvb, tlv_offset, 1, FALSE);
1220                         break;
1221                 case REG_TLV_T_43_MAC_HEADER_AND_EXTENDED_SUBHEADER_SUPPORT:
1222                         /* add TLV subtree */
1223                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "MAC header and extended subheader support %d", tvb_get_ntoh24(tvb, tlv_offset));
1224                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support, tvb, tlv_offset, 3, FALSE);
1225                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support, tvb, tlv_offset, 3, FALSE);
1226                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_cqich_allocation_request_header_support, tvb, tlv_offset, 3, FALSE);
1227                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_phy_channel_report_header_support, tvb, tlv_offset, 3, FALSE);
1228                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support, tvb, tlv_offset, 3, FALSE);
1229                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sn_report_header_support, tvb, tlv_offset, 3, FALSE);
1230                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_feedback_header_support, tvb, tlv_offset, 3, FALSE);
1231                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter, tvb, tlv_offset, 3, FALSE);
1232                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sdu_sn_parameter, tvb, tlv_offset, 3, FALSE);
1233                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_dl_sleep_control_extended_subheader, tvb, tlv_offset, 3, FALSE);
1234                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_feedback_request_extended_subheader, tvb, tlv_offset, 3, FALSE);
1235                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader, tvb, tlv_offset, 3, FALSE);
1236                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader, tvb, tlv_offset, 3, FALSE);
1237                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_mini_feedback_extended_subheader, tvb, tlv_offset, 3, FALSE);
1238                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sn_request_extended_subheader, tvb, tlv_offset, 3, FALSE);
1239                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_pdu_sn_short_extended_subheader, tvb, tlv_offset, 3, FALSE);
1240                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_pdu_sn_long_extended_subheader, tvb, tlv_offset, 3, FALSE);
1241                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_reserved, tvb, tlv_offset, 3, FALSE);
1242                         break;
1243                 case REG_REQ_BS_SWITCHING_TIMER:
1244                         /* add TLV subtree */
1245                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "BS switching timer (%d)", tvb_get_guint8(tvb, tlv_offset));
1246                         proto_tree_add_item(tlv_tree, hf_reg_req_min_time_for_intra_fa, tvb, tlv_offset, 1, FALSE);
1247                         proto_tree_add_item(tlv_tree, hf_reg_req_min_time_for_inter_fa, tvb, tlv_offset, 1, FALSE);
1248                         break;
1249                 case VENDOR_SPECIFIC_INFO:
1250                 case VENDOR_ID_ENCODING:
1251                 case CURRENT_TX_POWER:
1252                 case MAC_VERSION_ENCODING:
1253                 case CMAC_TUPLE:        /* Table 348b */
1254                         wimax_common_tlv_encoding_decoder(tvb_new_subset(tvb, offset, (tvb_len - offset), (tvb_len - offset)), pinfo, reg_req_tree);
1255                         break;
1256                 default:
1257                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, (tvb_len - tlv_offset), FALSE);
1258                         proto_tree_add_item(tlv_tree, hf_tlv_type, tvb, tlv_offset, (tvb_len - tlv_offset), FALSE);
1259                         break;
1260         }
1261 #endif
1262 }
1263
1264 /* Register Wimax Mac Payload Protocol and Dissector */
1265 void proto_register_mac_mgmt_msg_reg_req(void)
1266 {
1267         if (proto_mac_mgmt_msg_reg_req_decoder == -1)
1268         {
1269                 proto_mac_mgmt_msg_reg_req_decoder = proto_register_protocol (
1270                                                         "WiMax REG-REQ/RSP Messages", /* name */
1271                                                         "WiMax REG-REQ/RSP (reg)", /* short name */
1272                                                         "wmx.reg" /* abbrev */
1273                                                         );
1274
1275                 proto_register_field_array(proto_mac_mgmt_msg_reg_req_decoder, hf, array_length(hf));
1276                 proto_register_subtree_array(ett, array_length(ett));
1277         }
1278 }
1279
1280 /* Decode REG-REQ messages. */
1281 void dissect_mac_mgmt_msg_reg_req_decoder(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree)
1282 {
1283         guint offset = 0;
1284         guint tlv_offset;
1285         guint tvb_len, payload_type;
1286         proto_item *reg_req_item = NULL;
1287         proto_tree *reg_req_tree = NULL;
1288         proto_tree *tlv_tree = NULL;
1289         gboolean hmac_found = FALSE;
1290         tlv_info_t tlv_info;
1291         gint tlv_type;
1292         gint tlv_len;
1293
1294         /* Ensure the right payload type */
1295         payload_type = tvb_get_guint8(tvb, offset);
1296         if (payload_type != MAC_MGMT_MSG_REG_REQ)
1297         {
1298                 return;
1299         }
1300
1301         if (tree)
1302         {       /* we are being asked for details */
1303
1304                 /* Get the tvb reported length */
1305                 tvb_len =  tvb_reported_length(tvb);
1306                 /* display MAC payload type REG-REQ */
1307                 reg_req_item = proto_tree_add_protocol_format(tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tvb_len, "MAC Management Message, REG-REQ (6)");
1308                 /* add MAC REG-REQ subtree */
1309                 reg_req_tree = proto_item_add_subtree(reg_req_item, ett_mac_mgmt_msg_reg_req_decoder);
1310                 /* display the Message Type */
1311                 proto_tree_add_item(reg_req_tree, hf_reg_req_message_type, tvb, offset, 1, FALSE);
1312                 offset += 1;
1313
1314                 while(offset < tvb_len)
1315                 {
1316                         /* Get the TLV data. */
1317                         init_tlv_info(&tlv_info, tvb, offset);
1318                         /* get the TLV type */
1319                         tlv_type = get_tlv_type(&tlv_info);
1320                         /* get the TLV length */
1321                         tlv_len = get_tlv_length(&tlv_info);
1322                         if(tlv_type == -1 || tlv_len > MAX_TLV_LEN || tlv_len < 1)
1323                         {       /* invalid tlv info */
1324                                 if (pinfo->cinfo)
1325                                 {
1326                                         col_append_sep_str(pinfo->cinfo, COL_INFO, NULL, "REG-REQ TLV error");
1327                                 }
1328                                 proto_tree_add_item(reg_req_tree, hf_reg_invalid_tlv, tvb, offset, (tvb_len - offset), FALSE);
1329                                 break;
1330                         }
1331                         /* get the offset to the TLV data */
1332                         tlv_offset = offset + get_tlv_value_offset(&tlv_info);
1333
1334                         switch (tlv_type) {
1335                                 case REG_ARQ_PARAMETERS:
1336                                 case REG_SS_MGMT_SUPPORT:
1337                                 case REG_IP_MGMT_MODE:
1338                                 case REG_IP_VERSION:
1339                                 case REG_UL_TRANSPORT_CIDS_SUPPORTED:
1340                                 case REG_IP_PHS_SDU_ENCAP:
1341                                 case REG_MAX_CLASSIFIERS_SUPPORTED:
1342                                 case REG_PHS_SUPPORT:
1343                                 case REG_ARQ_SUPPORT:
1344                                 case REG_DSX_FLOW_CONTROL:
1345                                 case REG_MAC_CRC_SUPPORT:
1346                                 case REG_MCA_FLOW_CONTROL:
1347                                 case REG_MCAST_POLLING_CIDS:
1348                                 case REG_NUM_DL_TRANS_CID:
1349                                 case REG_MAC_ADDRESS:
1350 #ifdef WIMAX_16E_2005
1351                                 case REG_TLV_T_20_MAX_MAC_DATA_PER_FRAME_SUPPORT:
1352                                 case REG_TLV_T_21_PACKING_SUPPORT:
1353                                 case REG_TLV_T_22_MAC_EXTENDED_RTPS_SUPPORT:
1354                                 case REG_TLV_T_23_MAX_NUM_BURSTS_TRANSMITTED_CONCURRENTLY_TO_THE_MS:
1355                                 case REG_TLV_T_26_METHOD_FOR_ALLOCATING_IP_ADDR_SECONDARY_MGMNT_CONNECTION:
1356                                 case REG_TLV_T_27_HANDOVER_SUPPORTED:
1357                                 case REG_TLV_T_29_HO_PROCESS_OPTIMIZATION_MS_TIMER:
1358                                 case REG_TLV_T_31_MOBILITY_FEATURES_SUPPORTED:
1359                                 case REG_TLV_T_40_ARQ_ACK_TYPE:
1360                                 case REG_TLV_T_41_MS_HO_CONNECTIONS_PARAM_PROCESSING_TIME:
1361                                 case REG_TLV_T_42_MS_HO_TEK_PROCESSING_TIME:
1362                                 case REG_TLV_T_43_MAC_HEADER_AND_EXTENDED_SUBHEADER_SUPPORT:
1363                                 case REG_REQ_BS_SWITCHING_TIMER:
1364                                 case REG_POWER_SAVING_CLASS_CAPABILITY:
1365 #endif
1366                                         /* Decode REG-REQ sub-TLV's. */
1367                                         dissect_extended_tlv(reg_req_tree, tlv_type, tvb, tlv_offset, tlv_len, pinfo, offset, proto_mac_mgmt_msg_reg_req_decoder);
1368                                         break;
1369                                 case REG_REQ_SECONDARY_MGMT_CID:
1370                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_req_secondary_mgmt_cid, tvb, tlv_offset, 2, FALSE);
1371                                         proto_tree_add_item(tlv_tree, hf_reg_req_secondary_mgmt_cid, tvb, tlv_offset, 2, FALSE);
1372                                         break;
1373                                 case REG_REQ_TLV_T_32_SLEEP_MODE_RECOVERY_TIME:
1374                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_req_tlv_t_32_sleep_mode_recovery_time, tvb, tlv_offset, tlv_len, FALSE);
1375                                         proto_tree_add_item(tlv_tree, hf_reg_req_tlv_t_32_sleep_mode_recovery_time, tvb, tlv_offset, 1, FALSE);
1376                                         break;
1377                                 case REG_REQ_TLV_T_33_MS_PREV_IP_ADDR:
1378                                         if ( tlv_len == 4 ) {
1379                                                 tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_ms_previous_ip_address_v4, tvb, tlv_offset, tlv_len, FALSE);
1380                                                 proto_tree_add_item(tlv_tree, hf_ms_previous_ip_address_v4, tvb, tlv_offset, tlv_len, FALSE);
1381                                         } else if ( tlv_len == 16 ) {
1382                                                 tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_ms_previous_ip_address_v6, tvb, tlv_offset, tlv_len, FALSE);
1383                                                 proto_tree_add_item(tlv_tree, hf_ms_previous_ip_address_v6, tvb, tlv_offset, tlv_len, FALSE);
1384                                         }
1385                                         break;
1386                                 case REG_TLV_T_37_IDLE_MODE_TIMEOUT:
1387                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_idle_mode_timeout, tvb, tlv_offset, tlv_len, FALSE);
1388                                         proto_tree_add_item(tlv_tree, hf_idle_mode_timeout, tvb, tlv_offset, tlv_len, FALSE);
1389                                         break;
1390                                 case REG_REQ_TLV_T_45_MS_PERIODIC_RANGING_TIMER_INFO:
1391                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_req_tlv_t_45_ms_periodic_ranging_timer, tvb, tlv_offset, tlv_len, FALSE);
1392                                         proto_tree_add_item(tlv_tree, hf_reg_req_tlv_t_45_ms_periodic_ranging_timer, tvb, tlv_offset, tlv_len, FALSE);
1393                                         break;
1394                                 case REG_HANDOVER_INDICATION_READINESS_TIMER:
1395                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_46_handover_indication_readiness_timer, tvb, tlv_offset, tlv_len, FALSE);
1396                                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_46_handover_indication_readiness_timer, tvb, tlv_offset, tlv_len, FALSE);
1397                                         break;
1398
1399                                 case DSx_UPLINK_FLOW:
1400                                         /* display Uplink Service Flow Encodings info */
1401                                         /* add subtree */
1402                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, tlv_offset, tlv_len, "Uplink Service Flow Encodings (%u byte(s))", tlv_len);
1403                                         /* decode and display the DL Service Flow Encodings */
1404                                         wimax_service_flow_encodings_decoder(tvb_new_subset(tvb, tlv_offset, tlv_len, tlv_len), pinfo, tlv_tree);
1405                                         break;
1406                                 case DSx_DOWNLINK_FLOW:
1407                                         /* display Downlink Service Flow Encodings info */
1408                                         /* add subtree */
1409                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, tlv_offset, tlv_len, "Downlink Service Flow Encodings (%u byte(s))", tlv_len);
1410                                         /* decode and display the DL Service Flow Encodings */
1411                                         wimax_service_flow_encodings_decoder(tvb_new_subset(tvb, tlv_offset, tlv_len, tlv_len), pinfo, tlv_tree);
1412                                         break;
1413                                 case HMAC_TUPLE:        /* Table 348d */
1414                                         /* decode and display the HMAC Tuple */
1415                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, tlv_offset, tlv_len, "HMAC Tuple (%u byte(s))", tlv_len);
1416                                         wimax_hmac_tuple_decoder(tlv_tree, tvb, tlv_offset, tlv_len);
1417                                         hmac_found = TRUE;
1418                                         break;
1419                                 case CMAC_TUPLE:        /* Table 348b */
1420                                         /* decode and display the CMAC Tuple */
1421                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, tlv_offset, tlv_len, "CMAC Tuple (%u byte(s))", tlv_len);
1422                                         wimax_cmac_tuple_decoder(tlv_tree, tvb, tlv_offset, tlv_len);
1423                                         break;
1424                                 default:
1425                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_tlv_type, tvb, tlv_offset, tlv_len, FALSE);
1426                                         proto_tree_add_item(tlv_tree, hf_tlv_type, tvb, tlv_offset, tlv_len, FALSE);
1427                                         break;
1428                         }
1429                         /* update the offset */
1430                         offset = tlv_len + tlv_offset;
1431                 } /* End while() looping through the tvb. */
1432                 if (!hmac_found)
1433                         proto_item_append_text(reg_req_tree, " (HMAC Tuple is missing !)");
1434         }
1435 }