Use ENC_NA as proto_tree_add_item() encoding arg for FT_ETHER hf[] field type.
[obnox/wireshark/wip.git] / plugins / wimax / msg_reg_req.c
1 /* msg_reg_req.c
2  * WiMax MAC Management REG-REQ Message decoder
3  *
4  * Copyright (c) 2007 by Intel Corporation.
5  *
6  * Author: John R. Underwood <junderx@yahoo.com>
7  *
8  * $Id$
9  *
10  * Wireshark - Network traffic analyzer
11  * By Gerald Combs <gerald@wireshark.org>
12  * Copyright 1999 Gerald Combs
13  *
14  * This program is free software; you can redistribute it and/or
15  * modify it under the terms of the GNU General Public License
16  * as published by the Free Software Foundation; either version 2
17  * of the License, or (at your option) any later version.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22  * GNU General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, write to the Free Software
26  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
27  */
28
29 /* Include files */
30
31 #ifdef HAVE_CONFIG_H
32 #include "config.h"
33 #endif
34
35 #define WIMAX_16E_2005
36
37 #include <glib.h>
38 #include <epan/packet.h>
39 #include "crc.h"
40 #include "wimax_tlv.h"
41 #include "wimax_mac.h"
42 #include "wimax_utils.h"
43
44 extern gint proto_wimax;
45 extern gboolean include_cor2_changes;
46
47 gint proto_mac_mgmt_msg_reg_req_decoder = -1;
48 static gint ett_mac_mgmt_msg_reg_req_decoder = -1;
49
50 /* REG-REQ fields */
51 static gint hf_reg_ss_mgmt_support                   = -1;
52 static gint hf_reg_ip_mgmt_mode                      = -1;
53 static gint hf_reg_ip_version                        = -1;
54 static gint hf_reg_req_secondary_mgmt_cid            = -1;
55 static gint hf_reg_ul_cids                           = -1;
56 static gint hf_reg_max_classifiers                   = -1;
57 static gint hf_reg_phs                               = -1;
58 static gint hf_reg_arq                               = -1;
59 static gint hf_reg_dsx_flow_control                  = -1;
60 static gint hf_reg_mac_crc_support                   = -1;
61 static gint hf_reg_mca_flow_control                  = -1;
62 static gint hf_reg_mcast_polling_cids                = -1;
63 static gint hf_reg_num_dl_trans_cid                  = -1;
64 static gint hf_reg_mac_address                       = -1;
65 static gint hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame      = -1;
66 static gint hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame      = -1;
67 static gint hf_reg_tlv_t_21_packing_support                        = -1;
68 static gint hf_reg_tlv_t_22_mac_extended_rtps_support              = -1;
69 static gint hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms = -1;
70 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp     = -1;
71 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4 = -1;
72 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6   = -1;
73 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6     = -1;
74 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd     = -1;
75 static gint hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable          = -1;
76 static gint hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps = -1;
77 static gint hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map = -1;
78 static gint hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps       = -1;
79 static gint hf_reg_tlv_t_27_handover_mdho_ul_multiple              = -1;
80 static gint hf_reg_tlv_t_27_handover_reserved                      = -1;
81 static gint hf_reg_tlv_t_29_ho_process_opt_ms_timer                = -1;
82 static gint hf_reg_tlv_t_31_mobility_handover                      = -1;
83 static gint hf_reg_tlv_t_31_mobility_sleep_mode                    = -1;
84 static gint hf_reg_tlv_t_31_mobility_idle_mode                     = -1;
85 static gint hf_reg_req_tlv_t_32_sleep_mode_recovery_time           = -1;
86 static gint hf_ms_previous_ip_address_v4                           = -1;
87 static gint hf_ms_previous_ip_address_v6                           = -1;
88 static gint hf_idle_mode_timeout                                   = -1;
89 static gint hf_reg_req_tlv_t_45_ms_periodic_ranging_timer          = -1;
90 static gint hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry = -1;
91 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry = -1;
92 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry = -1;
93 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack = -1;
94 static gint hf_reg_tlv_t_40_arq_ack_type_reserved                  = -1;
95 static gint hf_reg_tlv_t_41_ho_connections_param_processing_time   = -1;
96 static gint hf_reg_tlv_t_42_ho_tek_processing_time                 = -1;
97 static gint hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support = -1;
98 static gint hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support = -1;
99 static gint hf_reg_tlv_t_43_cqich_allocation_request_header_support = -1;
100 static gint hf_reg_tlv_t_43_phy_channel_report_header_support      = -1;
101 static gint hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support = -1;
102 static gint hf_reg_tlv_t_43_sn_report_header_support               = -1;
103 static gint hf_reg_tlv_t_43_feedback_header_support                = -1;
104 static gint hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter = -1;
105 static gint hf_reg_tlv_t_43_sdu_sn_parameter                       = -1;
106 static gint hf_reg_tlv_t_43_dl_sleep_control_extended_subheader    = -1;
107 static gint hf_reg_tlv_t_43_feedback_request_extended_subheader    = -1;
108 static gint hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader  = -1;
109 static gint hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader  = -1;
110 static gint hf_reg_tlv_t_43_mini_feedback_extended_subheader       = -1;
111 static gint hf_reg_tlv_t_43_sn_request_extended_subheader          = -1;
112 static gint hf_reg_tlv_t_43_pdu_sn_short_extended_subheader        = -1;
113 static gint hf_reg_tlv_t_43_pdu_sn_long_extended_subheader         = -1;
114 static gint hf_reg_tlv_t_43_reserved                               = -1;
115 static gint hf_reg_tlv_t_46_handover_indication_readiness_timer    = -1;
116 static gint hf_reg_req_min_time_for_intra_fa                       = -1;
117 static gint hf_reg_req_min_time_for_inter_fa                       = -1;
118 static gint hf_reg_encap_atm_4                                     = -1;
119 static gint hf_reg_encap_ipv4_4                                      = -1;
120 static gint hf_reg_encap_ipv6_4                                      = -1;
121 static gint hf_reg_encap_802_3_4                                     = -1;
122 static gint hf_reg_encap_802_1q_4                                    = -1;
123 static gint hf_reg_encap_ipv4_802_3_4                                = -1;
124 static gint hf_reg_encap_ipv6_802_3_4                                = -1;
125 static gint hf_reg_encap_ipv4_802_1q_4                               = -1;
126 static gint hf_reg_encap_ipv6_802_1q_4                               = -1;
127 static gint hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4  = -1;
128 static gint hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4 = -1;
129 static gint hf_reg_encap_packet_ip_rohc_header_compression_4         = -1;
130 static gint hf_reg_encap_packet_ip_ecrtp_header_compression_4        = -1;
131 static gint hf_reg_encap_rsvd_4                                     = -1;
132 static gint hf_reg_encap_atm_2                                     = -1;
133 static gint hf_reg_encap_ipv4_2                                      = -1;
134 static gint hf_reg_encap_ipv6_2                                      = -1;
135 static gint hf_reg_encap_802_3_2                                     = -1;
136 static gint hf_reg_encap_802_1q_2                                    = -1;
137 static gint hf_reg_encap_ipv4_802_3_2                                = -1;
138 static gint hf_reg_encap_ipv6_802_3_2                                = -1;
139 static gint hf_reg_encap_ipv4_802_1q_2                               = -1;
140 static gint hf_reg_encap_ipv6_802_1q_2                               = -1;
141 static gint hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2  = -1;
142 static gint hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2 = -1;
143 static gint hf_reg_encap_packet_ip_rohc_header_compression_2         = -1;
144 static gint hf_reg_encap_packet_ip_ecrtp_header_compression_2        = -1;
145 static gint hf_reg_encap_rsvd_2                                     = -1;
146 static gint hf_tlv_type                                            = -1;
147 static gint hf_reg_invalid_tlv                                     = -1;
148 static gint hf_reg_power_saving_class_type_i                       = -1;
149 static gint hf_reg_power_saving_class_type_ii                      = -1;
150 static gint hf_reg_power_saving_class_type_iii                     = -1;
151 static gint hf_reg_multi_active_power_saving_classes               = -1;
152 static gint hf_reg_total_power_saving_class_instances              = -1;
153 static gint hf_reg_power_saving_class_reserved                     = -1;
154
155 static gint hf_reg_req_message_type                                = -1;
156
157 /* STRING RESOURCES */
158
159 static const true_false_string tfs_reg_ip_mgmt_mode = {
160     "IP-managed mode",
161     "Unmanaged mode"
162 };
163
164 static const true_false_string tfs_reg_ss_mgmt_support = {
165     "secondary management connection",
166     "no secondary management connection"
167 };
168
169 static const true_false_string tfs_arq_enable = {
170             "ARQ Requested/Accepted",
171                 "ARQ Not Requested/Accepted"
172 };
173
174 static const true_false_string tfs_arq_deliver_in_order = {
175             "Order of delivery is preserved",
176                 "Order of delivery is not preserved"
177 };
178
179 static const true_false_string tfs_reg_fbss_mdho_ho_disable = {
180     "Disable",
181     "Enable"
182 };
183
184 static const value_string vals_reg_ip_version[] = {
185     {0x1,                               "IPv4"},
186     {0x2,                               "IPV6"},
187     {0,                                 NULL}
188 };
189
190 static const value_string vals_reg_phs_support[] = {
191     {0,                                 "no PHS support"},
192     {1,                                 "ATM PHS"},
193     {2,                                 "Packet PHS"},
194     {3,                                 "ATM and Packet PHS"},
195     {0,                                 NULL}
196 };
197
198 static const true_false_string tfs_supported = {
199     "supported",
200     "unsupported"
201 };
202
203 static const true_false_string tfs_mac_crc_support = {
204     "MAC CRC Support (Default)",
205     "No MAC CRC Support"
206 };
207
208 static const value_string tfs_support[] = {
209     {0,                                 "not supported"},
210     {1,                                 "supported"},
211     {0,                                 NULL}
212 };
213
214 /* Decode REG-REQ sub-TLV's. */
215 void dissect_extended_tlv(proto_tree *reg_req_tree, gint tlv_type, tvbuff_t *tvb, guint tlv_offset, guint tlv_len, packet_info *pinfo, guint offset, gint proto_registry)
216 {
217         proto_item *tlv_item = NULL;
218         proto_tree *tlv_tree = NULL;
219         proto_tree *sub_tree = NULL;
220         guint tvb_len;
221         tlv_info_t tlv_info;
222         guint tlv_end;
223         guint length;
224         guint nblocks;
225
226         /* Get the tvb reported length */
227         tvb_len =  tvb_reported_length(tvb);
228
229         /* get the TLV information */
230         init_tlv_info(&tlv_info, tvb, offset);
231
232 #ifdef WIMAX_16E_2005
233         switch (tlv_type) {
234                 case REG_ARQ_PARAMETERS:
235                         /* display ARQ Service Flow Encodings info */
236                         /* add subtree */
237                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "ARQ Service Flow Encodings (%u byte(s))", tlv_len);
238                         /* decode and display the DL Service Flow Encodings */
239                         wimax_service_flow_encodings_decoder(tvb_new_subset(tvb, tlv_offset, tlv_len, tlv_len), pinfo, tlv_tree);
240                         break;
241                 case REG_SS_MGMT_SUPPORT:
242                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_ss_mgmt_support, tvb, tlv_offset, tlv_len, FALSE);
243                         proto_tree_add_item(tlv_tree, hf_reg_ss_mgmt_support, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
244                         break;
245                 case REG_IP_MGMT_MODE:
246                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_ip_mgmt_mode, tvb, tlv_offset, tlv_len, FALSE);
247                         proto_tree_add_item(tlv_tree, hf_reg_ip_mgmt_mode, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
248                         break;
249                 case REG_IP_VERSION:
250                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_ip_version, tvb, tlv_offset, tlv_len, FALSE);
251                         proto_tree_add_item(tlv_tree, hf_reg_ip_version, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
252                         break;
253                 case REG_UL_TRANSPORT_CIDS_SUPPORTED:
254                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_ul_cids, tvb, tlv_offset, tlv_len, FALSE);
255                         proto_tree_add_item(tlv_tree, hf_reg_ul_cids, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
256                         break;
257                         
258                 case REG_POWER_SAVING_CLASS_CAPABILITY:
259                         /* add TLV subtree */
260                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Power saving class capability (%d)", tvb_get_ntohs(tvb, tlv_offset));
261                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_i, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
262                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_ii, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
263                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_iii, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
264                         proto_tree_add_item(tlv_tree, hf_reg_multi_active_power_saving_classes, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
265                         proto_tree_add_item(tlv_tree, hf_reg_total_power_saving_class_instances, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
266                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_reserved, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
267                         break;
268                 case REG_IP_PHS_SDU_ENCAP:
269                         /* add TLV subtree */
270                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Classification/PHS options and SDU encapsulation support 0x%04x", tvb_get_ntohs(tvb, tlv_offset));
271
272 #ifdef WIMAX_16E_2005
273                         if (tlv_len == 2){
274                                 proto_tree_add_item(tlv_tree, hf_reg_encap_atm_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
275                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
276                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
277                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_3_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
278                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_1q_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
279                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_3_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
280                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_3_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
281                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_1q_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
282                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_1q_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
283                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
284                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
285                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_rohc_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
286                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_ecrtp_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
287                                 proto_tree_add_item(tlv_tree, hf_reg_encap_rsvd_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
288                         } else if(tlv_len == 4){
289                                 proto_tree_add_item(tlv_tree, hf_reg_encap_atm_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
290                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
291                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
292                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_3_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
293                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_1q_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
294                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_3_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
295                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_3_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
296                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_1q_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
297                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_1q_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
298                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
299                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
300                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_rohc_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
301                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_ecrtp_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
302                                 proto_tree_add_item(tlv_tree, hf_reg_encap_rsvd_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
303                         }
304 #endif
305                         break;
306                 case REG_MAX_CLASSIFIERS_SUPPORTED:
307                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_max_classifiers, tvb, tlv_offset, tlv_len, FALSE);
308                         proto_tree_add_item(tlv_tree, hf_reg_max_classifiers, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
309                         break;
310                 case REG_PHS_SUPPORT:
311                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_phs, tvb, tlv_offset, tlv_len, FALSE);
312                         proto_tree_add_item(tlv_tree, hf_reg_phs, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
313                         break;
314                 case REG_ARQ_SUPPORT:
315                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_arq, tvb, tlv_offset, tlv_len, FALSE);
316                         proto_tree_add_item(tlv_tree, hf_reg_arq, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
317                         break;
318                 case REG_DSX_FLOW_CONTROL:
319                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_dsx_flow_control, tvb, tlv_offset, tlv_len, FALSE);
320                         tlv_item = proto_tree_add_item(tlv_tree, hf_reg_dsx_flow_control, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
321                         if (tvb_get_guint8(tvb, tlv_offset) == 0) {
322                                 proto_item_append_text(tlv_item, " (no limit)");
323                         }
324                         break;
325                 case REG_MAC_CRC_SUPPORT:
326                         if (!include_cor2_changes) {
327                                 proto_tree_add_item(reg_req_tree, hf_reg_mac_crc_support, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
328                                 tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_mac_crc_support, tvb, tlv_offset, tlv_len, FALSE);
329                                 proto_tree_add_item(tlv_tree, hf_reg_mac_crc_support, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
330                         } else {
331                                 /* Unknown TLV Type */
332                                 tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, (tvb_len - tlv_offset), FALSE);
333                                 proto_tree_add_item(tlv_tree, hf_tlv_type, tvb, tlv_offset, (tvb_len - tlv_offset), ENC_NA);
334                         }
335                         break;
336                 case REG_MCA_FLOW_CONTROL:
337                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_mca_flow_control, tvb, tlv_offset, tlv_len, FALSE);
338                         tlv_item = proto_tree_add_item(tlv_tree, hf_reg_mca_flow_control, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
339                         if (tvb_get_guint8(tvb, tlv_offset) == 0) {
340                                 proto_item_append_text(tlv_item, " (no limit)");
341                         }
342                         break;
343                 case REG_MCAST_POLLING_CIDS:
344                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_mcast_polling_cids, tvb, tlv_offset, tlv_len, FALSE);
345                         proto_tree_add_item(tlv_tree, hf_reg_mcast_polling_cids, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
346                         break;
347                 case REG_NUM_DL_TRANS_CID:
348                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_num_dl_trans_cid, tvb, tlv_offset, tlv_len, FALSE);
349                         proto_tree_add_item(tlv_tree, hf_reg_num_dl_trans_cid, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
350                         break;
351                 case REG_MAC_ADDRESS:
352                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_mac_address, tvb, tlv_offset, tlv_len, FALSE);
353                         proto_tree_add_item(tlv_tree, hf_reg_mac_address, tvb, tlv_offset, 6, ENC_NA);
354                         break;
355                 case REG_TLV_T_20_MAX_MAC_DATA_PER_FRAME_SUPPORT:
356                         /* display Maximum MAC level data per frame info */
357                         /* add subtree */
358                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Maximum MAC level data per frame (%u byte(s))", tlv_len);
359                         /* decode and display Maximum MAC level data per frame for UL & DL */
360                         /* Set endpoint of the subTLVs (tlv_offset + length) */
361                         tlv_end = tlv_offset + tlv_len;
362                         /* process subTLVs */
363                         while ( tlv_offset < tlv_end )
364                         {       /* get the TLV information */
365                                 init_tlv_info(&tlv_info, tvb, tlv_offset);
366                                 /* get the TLV type */
367                                 tlv_type = get_tlv_type(&tlv_info);
368                                 /* get the TLV length */
369                                 length = get_tlv_length(&tlv_info);
370                                 if(tlv_type == -1 || length > MAX_TLV_LEN || length < 1)
371                                 {       /* invalid tlv info */
372                                         col_append_sep_str(pinfo->cinfo, COL_INFO, NULL, "REG-REQ TLV error");
373                                         proto_tree_add_item(reg_req_tree, hf_reg_invalid_tlv, tvb, offset, (tvb_len - offset), ENC_NA);
374                                         break;
375                                 }
376                                 /* update the offset */
377                                 tlv_offset += get_tlv_value_offset(&tlv_info);
378                                 nblocks = tvb_get_ntohs(tvb, tlv_offset);
379                                 switch (tlv_type)
380                                 {
381                                         case REG_TLV_T_20_1_MAX_MAC_LEVEL_DATA_PER_DL_FRAME:
382                                                 sub_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, tlv_tree, hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame, tvb, tlv_offset, length, FALSE);
383                                                 tlv_item = proto_tree_add_item(sub_tree, hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
384                                                 if ( nblocks == 0 )
385                                                 {
386                                                         proto_item_append_text(tlv_item, " (Unlimited bytes)");
387                                                 } else {
388                                                         proto_item_append_text(tlv_item, " (%d bytes)", 256 * nblocks);
389                                                 }
390                                                 break;
391                                         case REG_TLV_T_20_2_MAX_MAC_LEVEL_DATA_PER_UL_FRAME:
392                                                 sub_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, tlv_tree, hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame, tvb, tlv_offset, length, FALSE);
393                                                 tlv_item = proto_tree_add_item(sub_tree, hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
394                                                 if ( nblocks == 0 )
395                                                 {
396                                                         proto_item_append_text(tlv_item, " (Unlimited bytes)");
397                                                 } else {
398                                                         proto_item_append_text(tlv_item, " (%d bytes)", 256 * nblocks);
399                                                 }
400                                                 break;
401                                         default:
402                                                 sub_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, tlv_tree, hf_reg_invalid_tlv, tvb, tlv_offset, (tlv_end - tlv_offset), FALSE);
403                                                 proto_tree_add_item(sub_tree, hf_reg_invalid_tlv, tvb, tlv_offset, (tlv_end - tlv_offset), ENC_NA);
404                                                 break;
405                                 }
406                                 tlv_offset += length;
407                         }
408                         break;
409
410                 case REG_TLV_T_21_PACKING_SUPPORT:
411                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_21_packing_support, tvb, tlv_offset, tlv_len, FALSE);
412                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_21_packing_support, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
413                         break;
414                 case REG_TLV_T_22_MAC_EXTENDED_RTPS_SUPPORT:
415                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_22_mac_extended_rtps_support, tvb, tlv_offset, tlv_len, FALSE);
416                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_22_mac_extended_rtps_support, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
417                         break;
418                 case REG_TLV_T_23_MAX_NUM_BURSTS_TRANSMITTED_CONCURRENTLY_TO_THE_MS:
419                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms, tvb, tlv_offset, tlv_len, FALSE);
420                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
421                         break;
422                 case REG_TLV_T_26_METHOD_FOR_ALLOCATING_IP_ADDR_SECONDARY_MGMNT_CONNECTION:
423                         /* add TLV subtree */
424                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Method for allocating IP address for the secondary management connection (%d)", tvb_get_guint8(tvb, tlv_offset));
425                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
426                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
427                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
428                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
429                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
430                         break;
431                 case REG_TLV_T_27_HANDOVER_SUPPORTED:
432                         /* add TLV subtree */
433                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Handover Support (%d)", tvb_get_guint8(tvb, tlv_offset));
434                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
435                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
436                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
437                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
438                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_ul_multiple, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
439                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_reserved, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
440                         break;
441                 case REG_TLV_T_29_HO_PROCESS_OPTIMIZATION_MS_TIMER:
442                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_29_ho_process_opt_ms_timer, tvb, tlv_offset, tlv_len, FALSE);
443                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_29_ho_process_opt_ms_timer, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
444                         break;
445                 case REG_TLV_T_31_MOBILITY_FEATURES_SUPPORTED:
446                         /* add TLV subtree */
447                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "Mobility Features Supported (%d)", tvb_get_guint8(tvb, tlv_offset));
448                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_handover, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
449                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_sleep_mode, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
450                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_idle_mode, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
451                         break;
452                 case REG_TLV_T_40_ARQ_ACK_TYPE:
453                         /* add TLV subtree */
454                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "ARQ ACK Type 0x%02x", tvb_get_guint8(tvb, tlv_offset));
455                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
456                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
457                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
458                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
459                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_reserved, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
460                         break;
461                 case REG_TLV_T_41_MS_HO_CONNECTIONS_PARAM_PROCESSING_TIME:
462                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_41_ho_connections_param_processing_time, tvb, tlv_offset, tlv_len, FALSE);
463                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_41_ho_connections_param_processing_time, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
464                         break;
465                 case REG_TLV_T_42_MS_HO_TEK_PROCESSING_TIME:
466                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_42_ho_tek_processing_time, tvb, tlv_offset, tlv_len, FALSE);
467                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_42_ho_tek_processing_time, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
468                         break;
469                 case REG_TLV_T_43_MAC_HEADER_AND_EXTENDED_SUBHEADER_SUPPORT:
470                         /* add TLV subtree */
471                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "MAC header and extended subheader support %d", tvb_get_ntoh24(tvb, tlv_offset));
472                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
473                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
474                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_cqich_allocation_request_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
475                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_phy_channel_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
476                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
477                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sn_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
478                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_feedback_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
479                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
480                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sdu_sn_parameter, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
481                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_dl_sleep_control_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
482                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_feedback_request_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
483                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
484                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
485                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_mini_feedback_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
486                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sn_request_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
487                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_pdu_sn_short_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
488                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_pdu_sn_long_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
489                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_reserved, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
490                         break;
491                 case REG_REQ_BS_SWITCHING_TIMER:
492                         /* add TLV subtree */
493                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, tlv_len, "BS switching timer (%d)", tvb_get_guint8(tvb, tlv_offset));
494                         proto_tree_add_item(tlv_tree, hf_reg_req_min_time_for_intra_fa, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
495                         proto_tree_add_item(tlv_tree, hf_reg_req_min_time_for_inter_fa, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
496                         break;
497                 case VENDOR_SPECIFIC_INFO:
498                 case VENDOR_ID_ENCODING:
499                 case CURRENT_TX_POWER:
500                 case MAC_VERSION_ENCODING:
501                 case CMAC_TUPLE:        /* Table 348b */
502                         wimax_common_tlv_encoding_decoder(tvb_new_subset(tvb, offset, (tvb_len - offset), (tvb_len - offset)), pinfo, reg_req_tree);
503                         break;
504                 default:
505                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, tlv_offset, (tvb_len - tlv_offset), FALSE);
506                         proto_tree_add_item(tlv_tree, hf_tlv_type, tvb, tlv_offset, (tvb_len - tlv_offset), ENC_NA);
507                         break;
508         }
509 #endif
510 }
511
512
513 /* Decode REG-REQ messages. */
514 void dissect_mac_mgmt_msg_reg_req_decoder(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree)
515 {
516         guint offset = 0;
517         guint tlv_offset;
518         guint tvb_len, payload_type;
519         proto_item *reg_req_item = NULL;
520         proto_tree *reg_req_tree = NULL;
521         proto_tree *tlv_tree = NULL;
522         gboolean hmac_found = FALSE;
523         tlv_info_t tlv_info;
524         gint tlv_type;
525         gint tlv_len;
526
527         /* Ensure the right payload type */
528         payload_type = tvb_get_guint8(tvb, offset);
529         if (payload_type != MAC_MGMT_MSG_REG_REQ)
530         {
531                 return;
532         }
533
534         if (tree)
535         {       /* we are being asked for details */
536
537                 /* Get the tvb reported length */
538                 tvb_len =  tvb_reported_length(tvb);
539                 /* display MAC payload type REG-REQ */
540                 reg_req_item = proto_tree_add_protocol_format(tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tvb_len, "MAC Management Message, REG-REQ (6)");
541                 /* add MAC REG-REQ subtree */
542                 reg_req_tree = proto_item_add_subtree(reg_req_item, ett_mac_mgmt_msg_reg_req_decoder);
543                 /* display the Message Type */
544                 proto_tree_add_item(reg_req_tree, hf_reg_req_message_type, tvb, offset, 1, ENC_BIG_ENDIAN);
545                 offset += 1;
546
547                 while(offset < tvb_len)
548                 {
549                         /* Get the TLV data. */
550                         init_tlv_info(&tlv_info, tvb, offset);
551                         /* get the TLV type */
552                         tlv_type = get_tlv_type(&tlv_info);
553                         /* get the TLV length */
554                         tlv_len = get_tlv_length(&tlv_info);
555                         if(tlv_type == -1 || tlv_len > MAX_TLV_LEN || tlv_len < 1)
556                         {       /* invalid tlv info */
557                                 col_append_sep_str(pinfo->cinfo, COL_INFO, NULL, "REG-REQ TLV error");
558                                 proto_tree_add_item(reg_req_tree, hf_reg_invalid_tlv, tvb, offset, (tvb_len - offset), ENC_NA);
559                                 break;
560                         }
561                         /* get the offset to the TLV data */
562                         tlv_offset = offset + get_tlv_value_offset(&tlv_info);
563
564                         switch (tlv_type) {
565                                 case REG_ARQ_PARAMETERS:
566                                 case REG_SS_MGMT_SUPPORT:
567                                 case REG_IP_MGMT_MODE:
568                                 case REG_IP_VERSION:
569                                 case REG_UL_TRANSPORT_CIDS_SUPPORTED:
570                                 case REG_IP_PHS_SDU_ENCAP:
571                                 case REG_MAX_CLASSIFIERS_SUPPORTED:
572                                 case REG_PHS_SUPPORT:
573                                 case REG_ARQ_SUPPORT:
574                                 case REG_DSX_FLOW_CONTROL:
575                                 case REG_MAC_CRC_SUPPORT:
576                                 case REG_MCA_FLOW_CONTROL:
577                                 case REG_MCAST_POLLING_CIDS:
578                                 case REG_NUM_DL_TRANS_CID:
579                                 case REG_MAC_ADDRESS:
580 #ifdef WIMAX_16E_2005
581                                 case REG_TLV_T_20_MAX_MAC_DATA_PER_FRAME_SUPPORT:
582                                 case REG_TLV_T_21_PACKING_SUPPORT:
583                                 case REG_TLV_T_22_MAC_EXTENDED_RTPS_SUPPORT:
584                                 case REG_TLV_T_23_MAX_NUM_BURSTS_TRANSMITTED_CONCURRENTLY_TO_THE_MS:
585                                 case REG_TLV_T_26_METHOD_FOR_ALLOCATING_IP_ADDR_SECONDARY_MGMNT_CONNECTION:
586                                 case REG_TLV_T_27_HANDOVER_SUPPORTED:
587                                 case REG_TLV_T_29_HO_PROCESS_OPTIMIZATION_MS_TIMER:
588                                 case REG_TLV_T_31_MOBILITY_FEATURES_SUPPORTED:
589                                 case REG_TLV_T_40_ARQ_ACK_TYPE:
590                                 case REG_TLV_T_41_MS_HO_CONNECTIONS_PARAM_PROCESSING_TIME:
591                                 case REG_TLV_T_42_MS_HO_TEK_PROCESSING_TIME:
592                                 case REG_TLV_T_43_MAC_HEADER_AND_EXTENDED_SUBHEADER_SUPPORT:
593                                 case REG_REQ_BS_SWITCHING_TIMER:
594                                 case REG_POWER_SAVING_CLASS_CAPABILITY:
595 #endif
596                                         /* Decode REG-REQ sub-TLV's. */
597                                         dissect_extended_tlv(reg_req_tree, tlv_type, tvb, tlv_offset, tlv_len, pinfo, offset, proto_mac_mgmt_msg_reg_req_decoder);
598                                         break;
599                                 case REG_REQ_SECONDARY_MGMT_CID:
600                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_req_secondary_mgmt_cid, tvb, tlv_offset, 2, FALSE);
601                                         proto_tree_add_item(tlv_tree, hf_reg_req_secondary_mgmt_cid, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
602                                         break;
603                                 case REG_REQ_TLV_T_32_SLEEP_MODE_RECOVERY_TIME:
604                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_req_tlv_t_32_sleep_mode_recovery_time, tvb, tlv_offset, tlv_len, FALSE);
605                                         proto_tree_add_item(tlv_tree, hf_reg_req_tlv_t_32_sleep_mode_recovery_time, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
606                                         break;
607                                 case REG_REQ_TLV_T_33_MS_PREV_IP_ADDR:
608                                         if ( tlv_len == 4 ) {
609                                                 tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_ms_previous_ip_address_v4, tvb, tlv_offset, tlv_len, FALSE);
610                                                 proto_tree_add_item(tlv_tree, hf_ms_previous_ip_address_v4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
611                                         } else if ( tlv_len == 16 ) {
612                                                 tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_ms_previous_ip_address_v6, tvb, tlv_offset, tlv_len, FALSE);
613                                                 proto_tree_add_item(tlv_tree, hf_ms_previous_ip_address_v6, tvb, tlv_offset, tlv_len, ENC_NA);
614                                         }
615                                         break;
616                                 case REG_TLV_T_37_IDLE_MODE_TIMEOUT:
617                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_idle_mode_timeout, tvb, tlv_offset, tlv_len, FALSE);
618                                         proto_tree_add_item(tlv_tree, hf_idle_mode_timeout, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
619                                         break;
620                                 case REG_REQ_TLV_T_45_MS_PERIODIC_RANGING_TIMER_INFO:
621                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_req_tlv_t_45_ms_periodic_ranging_timer, tvb, tlv_offset, tlv_len, FALSE);
622                                         proto_tree_add_item(tlv_tree, hf_reg_req_tlv_t_45_ms_periodic_ranging_timer, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
623                                         break;
624                                 case REG_HANDOVER_INDICATION_READINESS_TIMER:
625                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_reg_tlv_t_46_handover_indication_readiness_timer, tvb, tlv_offset, tlv_len, FALSE);
626                                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_46_handover_indication_readiness_timer, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
627                                         break;
628
629                                 case DSx_UPLINK_FLOW:
630                                         /* display Uplink Service Flow Encodings info */
631                                         /* add subtree */
632                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, tlv_offset, tlv_len, "Uplink Service Flow Encodings (%u byte(s))", tlv_len);
633                                         /* decode and display the DL Service Flow Encodings */
634                                         wimax_service_flow_encodings_decoder(tvb_new_subset(tvb, tlv_offset, tlv_len, tlv_len), pinfo, tlv_tree);
635                                         break;
636                                 case DSx_DOWNLINK_FLOW:
637                                         /* display Downlink Service Flow Encodings info */
638                                         /* add subtree */
639                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, tlv_offset, tlv_len, "Downlink Service Flow Encodings (%u byte(s))", tlv_len);
640                                         /* decode and display the DL Service Flow Encodings */
641                                         wimax_service_flow_encodings_decoder(tvb_new_subset(tvb, tlv_offset, tlv_len, tlv_len), pinfo, tlv_tree);
642                                         break;
643                                 case HMAC_TUPLE:        /* Table 348d */
644                                         /* decode and display the HMAC Tuple */
645                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, tlv_offset, tlv_len, "HMAC Tuple (%u byte(s))", tlv_len);
646                                         wimax_hmac_tuple_decoder(tlv_tree, tvb, tlv_offset, tlv_len);
647                                         hmac_found = TRUE;
648                                         break;
649                                 case CMAC_TUPLE:        /* Table 348b */
650                                         /* decode and display the CMAC Tuple */
651                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, tlv_offset, tlv_len, "CMAC Tuple (%u byte(s))", tlv_len);
652                                         wimax_cmac_tuple_decoder(tlv_tree, tvb, tlv_offset, tlv_len);
653                                         break;
654                                 default:
655                                         tlv_tree = add_tlv_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, hf_tlv_type, tvb, tlv_offset, tlv_len, FALSE);
656                                         proto_tree_add_item(tlv_tree, hf_tlv_type, tvb, tlv_offset, tlv_len, ENC_NA);
657                                         break;
658                         }
659                         /* update the offset */
660                         offset = tlv_len + tlv_offset;
661                 } /* End while() looping through the tvb. */
662                 if (!hmac_found)
663                         proto_item_append_text(reg_req_tree, " (HMAC Tuple is missing !)");
664         }
665 }
666
667 /* Register Wimax Mac Payload Protocol and Dissector */
668 void proto_register_mac_mgmt_msg_reg_req(void)
669 {
670         /* REG-REQ fields display */
671         static hf_register_info hf[] =
672         {
673                 {
674                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp,
675                         {
676                                 "DHCP", "wmx.reg.alloc_sec_mgmt_dhcp",
677                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
678                         }
679                 },
680                 {
681                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6,
682                         {
683                                 "DHCPv6", "wmx.reg.alloc_sec_mgmt_dhcpv6",
684                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
685                         }
686                 },
687                 {
688                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6,
689                         {
690                                 "IPv6 Stateless Address Autoconfiguration", "wmx.reg.alloc_sec_mgmt_ipv6",
691                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, NULL, HFILL
692                         }
693                 },
694                 {
695                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4,
696                         {
697                                 "Mobile IPv4", "wmx.reg.alloc_sec_mgmt_mobile_ipv4",
698                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
699                         }
700                 },
701                 {
702                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd,
703                         {
704                                 "Reserved", "wmx.reg.alloc_sec_mgmt_rsvd",
705                                 FT_UINT8, BASE_DEC, NULL, 0xF0, NULL, HFILL
706                         }
707                 },
708                 {
709                         &hf_reg_arq,
710                         {
711                                 "ARQ support", "wmx.reg.arq",
712                                 FT_BOOLEAN, BASE_NONE, TFS(&tfs_supported), 0x0, NULL, HFILL
713                         }
714                 },
715                 {
716                         &hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry,
717                         {
718                                 "Cumulative ACK entry", "wmx.reg.arq_ack_type_cumulative_ack_entry",
719                                 FT_UINT8, BASE_DEC, NULL, 0x2, NULL, HFILL
720                         }
721                 },
722                 {
723                         &hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack,
724                         {
725                                 "Cumulative ACK with Block Sequence ACK", "wmx.reg.arq_ack_type_cumulative_ack_with_block_sequence_ack",
726                                 FT_UINT8, BASE_DEC, NULL, 0x8, NULL, HFILL
727                         }
728                 },
729                 {
730                         &hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry,
731                         {
732                                 "Cumulative with Selective ACK entry", "wmx.reg.arq_ack_type_cumulative_with_selective_ack_entry",
733                                 FT_UINT8, BASE_DEC, NULL, 0x4, NULL, HFILL
734                         }
735                 },
736                 {
737                         &hf_reg_tlv_t_40_arq_ack_type_reserved,
738                         {
739                                 "Reserved", "wmx.reg.arq_ack_type_reserved",
740                                 FT_UINT8, BASE_DEC, NULL, 0xf0, NULL, HFILL
741                         }
742                 },
743                 {
744                         &hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry,
745                         {
746                                 "Selective ACK entry", "wmx.reg.arq_ack_type_selective_ack_entry",
747                                 FT_UINT8, BASE_DEC, NULL, 0x1, NULL, HFILL
748                         }
749                 },
750                 {
751                         &hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support,
752                         {
753                                 "Bandwidth request and CINR report header support", "wmx.reg.bandwidth_request_cinr_report_header_support",
754                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x2, NULL, HFILL
755                         }
756                 },
757                 {
758                         &hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support,
759                         {
760                                 "Bandwidth request and uplink sleep control header support", "wmx.reg.bandwidth_request_ul_sleep_control_header_support",
761                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x10, NULL, HFILL
762                         }
763                 },
764                 {
765                         &hf_reg_tlv_t_43_cqich_allocation_request_header_support,
766                         {
767                                 "CQICH Allocation Request header support", "wmx.reg.cqich_allocation_request_header_support",
768                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x4, NULL, HFILL
769                         }
770                 },
771                 {
772                         &hf_reg_tlv_t_43_dl_sleep_control_extended_subheader,
773                         {
774                                 "Downlink sleep control extended subheader", "wmx.reg.dl_sleep_control_extended_subheader",
775                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x800, NULL, HFILL
776                         }
777                 },
778                 {
779                         &hf_reg_dsx_flow_control,
780                         {
781                                 "DSx flow control", "wmx.reg.dsx_flow_control",
782                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
783                         }
784                 },
785                 /* When REG-REQ TLV 7 is length 2 */
786                 {
787                         &hf_reg_encap_802_1q_2,
788                         {
789                                 "Packet, 802.1Q VLAN", "wmx.reg.encap_802_1q",
790                                 FT_UINT16, BASE_HEX, NULL, 0x0010, NULL, HFILL
791                         }
792                 },
793                 {
794                         &hf_reg_encap_802_3_2,
795                         {
796                                 "Packet, 802.3/Ethernet", "wmx.reg.encap_802_3",
797                                 FT_UINT16, BASE_HEX, NULL, 0x00000008, NULL, HFILL
798                         }
799                 },
800                 {
801                         &hf_reg_encap_atm_2,
802                         {
803                                 "ATM", "wmx.reg.encap_atm",
804                                 FT_UINT16, BASE_HEX, NULL, 0x00000001, NULL, HFILL
805                         }
806                 },
807                 {
808                         &hf_reg_encap_ipv4_2,
809                         {
810                                 "Packet, IPv4", "wmx.reg.encap_ipv4",
811                                 FT_UINT16, BASE_HEX, NULL, 0x00000002, NULL, HFILL
812                         }
813                 },
814                 {
815                         &hf_reg_encap_ipv6_2,
816                         {
817                                 "Packet, IPv6", "wmx.reg.encap_ipv6",
818                                 FT_UINT16, BASE_HEX, NULL, 0x00000004, NULL, HFILL
819                         }
820                 },
821                 {
822                         &hf_reg_encap_ipv4_802_1q_2,
823                         {
824                                 "Packet, IPv4 over 802.1Q VLAN", "wmx.reg.encap_ipv4_802_1q",
825                                 FT_UINT16, BASE_HEX, NULL, 0x00000080, NULL, HFILL
826                         }
827                 },
828                 {
829                         &hf_reg_encap_ipv4_802_3_2,
830                         {
831                                 "Packet, IPv4 over 802.3/Ethernet", "wmx.reg.encap_ipv4_802_3",
832                                 FT_UINT16, BASE_HEX, NULL, 0x00000020, NULL, HFILL
833                         }
834                 },
835                 {
836                         &hf_reg_encap_ipv6_802_1q_2,
837                         {
838                                 "Packet, IPv6 over 802.1Q VLAN", "wmx.reg.encap_ipv6_802_1q",
839                                 FT_UINT16, BASE_HEX, NULL, 0x00000100, NULL, HFILL
840                         }
841                 },
842                 {
843                         &hf_reg_encap_ipv6_802_3_2,
844                         {
845                                 "Packet, IPv6 over 802.3/Ethernet", "wmx.reg.encap_ipv6_802_3",
846                                 FT_UINT16, BASE_HEX, NULL, 0x00000040, NULL, HFILL
847                         }
848                 },
849                 {
850                         &hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2,
851                         {
852                                 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ECRTP header compression", "wmx.reg.encap_packet_802_3_ethernet_and_ecrtp_header_compression",
853                                 FT_UINT16, BASE_HEX, NULL, 0x00000400, NULL, HFILL
854                         }
855                 },
856                 {
857                         &hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2,
858                         {
859                                 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ROHC header compression", "wmx.reg.encap_packet_802_3_ethernet_and_rohc_header_compression",
860                                 FT_UINT16, BASE_HEX, NULL, 0x00000200, NULL, HFILL
861                         }
862                 },
863                 {
864                         &hf_reg_encap_packet_ip_ecrtp_header_compression_2,
865                         {
866                                 "Packet, IP (v4 or v6) with ECRTP header compression", "wmx.reg.encap_packet_ip_ecrtp_header_compression",
867                                 FT_UINT16, BASE_HEX, NULL, 0x00001000, NULL, HFILL
868                         }
869                 },
870                 {
871                         &hf_reg_encap_packet_ip_rohc_header_compression_2,
872                         {
873                                 "Packet, IP (v4 or v6) with ROHC header compression", "wmx.reg.encap_packet_ip_rohc_header_compression",
874                                 FT_UINT16, BASE_HEX, NULL, 0x00000800, NULL, HFILL
875                         }
876                 },
877                 {
878                         &hf_reg_encap_rsvd_2,
879                         {
880                                 "Reserved", "wmx.reg.encap_rsvd",
881                                 FT_UINT16, BASE_HEX, NULL, 0x0000E000, NULL, HFILL
882                         }
883                 },
884                 /* When REG-REQ TLV 7 is length 4 */
885                 {
886                         &hf_reg_encap_802_1q_4,
887                         {
888                                 "Packet, 802.1Q VLAN", "wmx.reg.encap_802_1q",
889                                 FT_UINT32, BASE_HEX, NULL, 0x0010, NULL, HFILL
890                         }
891                 },
892                 {
893                         &hf_reg_encap_802_3_4,
894                         {
895                                 "Packet, 802.3/Ethernet", "wmx.reg.encap_802_3",
896                                 FT_UINT32, BASE_HEX, NULL, 0x00000008, NULL, HFILL
897                         }
898                 },
899                 {
900                         &hf_reg_encap_atm_4,
901                         {
902                                 "ATM", "wmx.reg.encap_atm",
903                                 FT_UINT32, BASE_HEX, NULL, 0x00000001, NULL, HFILL
904                         }
905                 },
906                 {
907                         &hf_reg_encap_ipv4_4,
908                         {
909                                 "Packet, IPv4", "wmx.reg.encap_ipv4",
910                                 FT_UINT32, BASE_HEX, NULL, 0x00000002, NULL, HFILL
911                         }
912                 },
913                 {
914                         &hf_reg_encap_ipv4_802_1q_4,
915                         {
916                                 "Packet, IPv4 over 802.1Q VLAN", "wmx.reg.encap_ipv4_802_1q",
917                                 FT_UINT32, BASE_HEX, NULL, 0x00000080, NULL, HFILL
918                         }
919                 },
920                 {
921                         &hf_reg_encap_ipv4_802_3_4,
922                         {
923                                 "Packet, IPv4 over 802.3/Ethernet", "wmx.reg.encap_ipv4_802_3",
924                                 FT_UINT32, BASE_HEX, NULL, 0x00000020, NULL, HFILL
925                         }
926                 },
927                 {
928                         &hf_reg_encap_ipv6_4,
929                         {
930                                 "Packet, IPv6", "wmx.reg.encap_ipv6",
931                                 FT_UINT32, BASE_HEX, NULL, 0x00000004, NULL, HFILL
932                         }
933                 },
934                 {
935                         &hf_reg_encap_ipv6_802_1q_4,
936                         {
937                                 "Packet, IPv6 over 802.1Q VLAN", "wmx.reg.encap_ipv6_802_1q",
938                                 FT_UINT32, BASE_HEX, NULL, 0x00000100, NULL, HFILL
939                         }
940                 },
941                 {
942                         &hf_reg_encap_ipv6_802_3_4,
943                         {
944                                 "Packet, IPv6 over 802.3/Ethernet", "wmx.reg.encap_ipv6_802_3",
945                                 FT_UINT32, BASE_HEX, NULL, 0x00000040, NULL, HFILL
946                         }
947                 },
948                 {
949                         &hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4,
950                         {
951                                 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ECRTP header compression", "wmx.reg.encap_packet_802_3_ethernet_and_ecrtp_header_compression",
952                                 FT_UINT32, BASE_HEX, NULL, 0x00000400, NULL, HFILL
953                         }
954                 },
955                 {
956                         &hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4,
957                         {
958                                 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ROHC header compression", "wmx.reg.encap_packet_802_3_ethernet_and_rohc_header_compression",
959                                 FT_UINT32, BASE_HEX, NULL, 0x00000200, NULL, HFILL
960                         }
961                 },
962                 {
963                         &hf_reg_encap_packet_ip_ecrtp_header_compression_4,
964                         {
965                                 "Packet, IP (v4 or v6) with ECRTP header compression", "wmx.reg.encap_packet_ip_ecrtp_header_compression",
966                                 FT_UINT32, BASE_HEX, NULL, 0x00001000, NULL, HFILL
967                         }
968                 },
969                 {
970                         &hf_reg_encap_packet_ip_rohc_header_compression_4,
971                         {
972                                 "Packet, IP (v4 or v6) with ROHC header compression", "wmx.reg.encap_packet_ip_rohc_header_compression",
973                                 FT_UINT32, BASE_HEX, NULL, 0x00000800, NULL, HFILL
974                         }
975                 },
976                 {
977                         &hf_reg_encap_rsvd_4,
978                         {
979                                 "Reserved", "wmx.reg.encap_rsvd",
980                                 FT_UINT32, BASE_HEX, NULL, 0xFFFFE000, NULL, HFILL
981                         }
982                 },
983                 {
984                         &hf_reg_tlv_t_22_mac_extended_rtps_support,
985                         {
986                                 "MAC extended rtPS support", "wmx.reg.ext_rtps_support",
987                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
988                         }
989                 },
990                 {
991                         &hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps,
992                         {
993                                 "FBSS/MDHO DL RF Combining with monitoring MAPs from active BSs", "wmx.reg.fbss_mdho_dl_rf_combining",
994                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
995                         }
996                 },
997                 {
998                         &hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support,
999                         {
1000                                 "Bandwidth request and UL Tx Power Report header support",
1001                                 "wimax.reg.bandwidth_request_ul_tx_pwr_report_header_support",
1002                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x1, NULL, HFILL
1003                         }
1004                 },
1005                 {
1006                         &hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable,
1007                         {
1008                                 "MDHO/FBSS HO. BS ignore all other bits when set to 1", "wmx.reg.fbss_mdho_ho_disable",
1009                                 FT_BOOLEAN, 8, TFS(&tfs_reg_fbss_mdho_ho_disable), 0x01, NULL, HFILL
1010                         }
1011                 },
1012                 {
1013                         &hf_reg_tlv_t_43_feedback_header_support,
1014                         {
1015                                 "Feedback header support", "wmx.reg.feedback_header_support",
1016                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x40, NULL, HFILL
1017                         }
1018                 },
1019                 {
1020                         &hf_reg_tlv_t_43_feedback_request_extended_subheader,
1021                         {
1022                                 "Feedback request extended subheader", "wmx.reg.feedback_request_extended_subheader",
1023                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x1000, NULL, HFILL
1024                         }
1025                 },
1026                 {
1027                         &hf_reg_tlv_t_46_handover_indication_readiness_timer,
1028                         {
1029                                 "Handover indication readiness timer", "wmx.reg.handover_indication_readiness_timer",
1030                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1031                         }
1032                 },
1033                 {
1034                         &hf_reg_tlv_t_27_handover_reserved,
1035                         {
1036                                 "Reserved", "wmx.reg.handover_reserved",
1037                                 FT_UINT8, BASE_DEC, NULL, 0xE0, NULL, HFILL
1038                         }
1039                 },
1040                 {
1041                         &hf_reg_tlv_t_41_ho_connections_param_processing_time,
1042                         {
1043                                 "MS HO connections parameters processing time", "wmx.reg.ho_connections_param_processing_time",
1044                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1045                         }
1046                 },
1047                 {
1048                         &hf_reg_tlv_t_29_ho_process_opt_ms_timer,
1049                         {
1050                                 "HO Process Optimization MS Timer", "wmx.reg.ho_process_opt_ms_timer",
1051                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1052                         }
1053                 },
1054                 {
1055                         &hf_reg_tlv_t_42_ho_tek_processing_time,
1056                         {
1057                                 "MS HO TEK processing time", "wmx.reg.ho_tek_processing_time",
1058                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1059                         }
1060                 },
1061                 {
1062                         &hf_idle_mode_timeout,
1063                         {
1064                                 "Idle Mode Timeout", "wmx.reg.idle_mode_timeout",
1065                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1066                         }
1067                 },
1068                 {
1069                         &hf_reg_ip_mgmt_mode,
1070                         {
1071                                 "IP management mode", "wmx.reg.ip_mgmt_mode",
1072                                 FT_BOOLEAN, BASE_NONE, TFS(&tfs_reg_ip_mgmt_mode), 0x0, NULL, HFILL
1073                         }
1074                 },
1075                 {
1076                         &hf_reg_ip_version,
1077                         {
1078                                 "IP version", "wmx.reg.ip_version",
1079                                 FT_UINT8, BASE_HEX, VALS(vals_reg_ip_version), 0x0, NULL, HFILL
1080                         }
1081                 },
1082                 {
1083                         &hf_reg_mac_address,
1084                         {
1085                                 "MAC Address of the SS", "wmx.reg.mac_address",
1086                                 FT_ETHER, BASE_NONE, NULL, 0x0, NULL, HFILL
1087                         }
1088                 },
1089                 {
1090                         &hf_reg_mac_crc_support,
1091                         {
1092                                 "MAC CRC", "wmx.reg.mac_crc_support",
1093                                 FT_BOOLEAN, BASE_NONE, TFS(&tfs_mac_crc_support), 0x0, NULL, HFILL
1094                         }
1095                 },
1096                 {
1097                         &hf_reg_max_classifiers,
1098                         {
1099                                 "Maximum number of classification rules", "wmx.reg.max_classifiers",
1100                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1101                         }
1102                 },
1103                 {
1104                         &hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms,
1105                         {
1106                                 "Maximum number of bursts transmitted concurrently to the MS", "wmx.reg.max_num_bursts_to_ms",
1107                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1108                         }
1109                 },
1110                 {
1111                         &hf_reg_mca_flow_control,
1112                         {
1113                                 "MCA flow control", "wmx.reg.mca_flow_control",
1114                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1115                         }
1116                 },
1117                 {
1118                         &hf_reg_mcast_polling_cids,
1119                         {
1120                                 "Multicast polling group CID support", "wmx.reg.mcast_polling_cids",
1121                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1122                         }
1123                 },
1124                 {
1125                         &hf_reg_tlv_t_27_handover_mdho_ul_multiple,
1126                         {
1127                                 "MDHO UL Multiple transmission", "wmx.reg.mdh_ul_multiple",
1128                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x10, NULL, HFILL
1129                         }
1130                 },
1131                 {
1132                         &hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps,
1133                         {
1134                                 "MDHO DL soft combining with monitoring MAPs from active BSs", "wmx.reg.mdho_dl_monitor_maps",
1135                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, NULL, HFILL
1136                         }
1137                 },
1138                 {
1139                         &hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map,
1140                         {
1141                                 "MDHO DL soft Combining with monitoring single MAP from anchor BS", "wmx.reg.mdho_dl_monitor_single_map",
1142                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
1143                         }
1144                 },
1145                 {
1146                         &hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader,
1147                         {
1148                                 "MIMO mode feedback request extended subheader", "wmx.reg.mimo_mode_feedback_request_extended_subheader",
1149                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x2000, NULL, HFILL
1150                         }
1151                 },
1152                 {
1153                         &hf_reg_tlv_t_43_mini_feedback_extended_subheader,
1154                         {
1155                                 "Mini-feedback extended subheader", "wmx.reg.mini_feedback_extended_subheader",
1156                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x8000, NULL, HFILL
1157                         }
1158                 },
1159                 {
1160                         &hf_reg_tlv_t_31_mobility_handover,
1161                         {
1162                                 "Mobility (handover)", "wmx.reg.mobility_handover",
1163                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
1164                         }
1165                 },
1166                 {
1167                         &hf_reg_tlv_t_31_mobility_idle_mode,
1168                         {
1169                                 "Idle mode", "wmx.reg.mobility_idle_mode",
1170                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
1171                         }
1172                 },
1173                 {
1174                         &hf_reg_tlv_t_31_mobility_sleep_mode,
1175                         {
1176                                 "Sleep mode", "wmx.reg.mobility_sleep_mode",
1177                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
1178                         }
1179                 },
1180                 {
1181                         &hf_reg_num_dl_trans_cid,
1182                         {
1183                                 "Number of Downlink transport CIDs the SS can support", "wmx.reg.dl_cids_supported",
1184                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1185                         }
1186                 },
1187                 {
1188                         &hf_reg_tlv_t_21_packing_support,
1189                         {
1190                                 "Packing support", "wmx.reg.packing.support",
1191                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
1192                         }
1193                 },
1194                 {
1195                         &hf_reg_tlv_t_43_pdu_sn_long_extended_subheader,
1196                         {
1197                                 "PDU SN (long) extended subheader", "wmx.reg.pdu_sn_long_extended_subheader",
1198                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x40000, NULL, HFILL
1199                         }
1200                 },
1201                 {
1202                         &hf_reg_tlv_t_43_pdu_sn_short_extended_subheader,
1203                         {
1204                                 "PDU SN (short) extended subheader", "wmx.reg.pdu_sn_short_extended_subheader",
1205                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x20000, NULL, HFILL
1206                         }
1207                 },
1208                 {
1209                         &hf_reg_phs,
1210                         {
1211                                 "PHS support", "wmx.reg.phs",
1212                                 FT_UINT8, BASE_DEC, VALS(vals_reg_phs_support), 0x0, NULL, HFILL
1213                         }
1214                 },
1215                 {
1216                         &hf_reg_tlv_t_43_phy_channel_report_header_support,
1217                         {
1218                                 "PHY channel report header support", "wmx.reg.phy_channel_report_header_support",
1219                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x8, NULL, HFILL
1220                         }
1221                 },
1222                 {
1223                         &hf_reg_tlv_t_43_reserved,
1224                         {
1225                                 "Reserved", "wmx.reg.reserved",
1226                                 FT_UINT24, BASE_DEC, NULL, 0xf80000, NULL, HFILL
1227                         }
1228                 },
1229                 {
1230                         &hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter,
1231                         {
1232                                 "SDU_SN extended subheader support", "wmx.reg.sdu_sn_extended_subheader_support",
1233                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x80, NULL, HFILL
1234                         }
1235                 },
1236                 {
1237                         &hf_reg_tlv_t_43_sdu_sn_parameter,
1238                         {
1239                                 "SDU_SN parameter", "wmx.reg.sdu_sn_parameter",
1240                                 FT_UINT24, BASE_DEC, NULL, 0x700, NULL, HFILL
1241                         }
1242                 },
1243                 {
1244                         &hf_reg_tlv_t_43_sn_report_header_support,
1245                         {
1246                                 "SN report header support", "wmx.reg.sn_report_header_support",
1247                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x20, NULL, HFILL
1248                         }
1249                 },
1250                 {
1251                         &hf_reg_tlv_t_43_sn_request_extended_subheader,
1252                         {
1253                                 "SN request extended subheader", "wmx.reg.sn_request_extended_subheader",
1254                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x10000, NULL, HFILL
1255                         }
1256                 },
1257                 {
1258                         &hf_reg_ss_mgmt_support,
1259                         {
1260                                 "SS management support", "wmx.reg.ss_mgmt_support",
1261                                 FT_BOOLEAN, BASE_NONE, TFS(&tfs_reg_ss_mgmt_support), 0x0, NULL, HFILL
1262                         }
1263                 },
1264                 {
1265                         &hf_reg_ul_cids,
1266                         {
1267                                 "Number of Uplink transport CIDs the SS can support", "wmx.reg.ul_cids_supported",
1268                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1269                         }
1270                 },
1271                 {
1272                         &hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader,
1273                         {
1274                                 "UL Tx power report extended subheader", "wmx.reg.ul_tx_power_report_extended_subheader",
1275                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x4000, NULL, HFILL
1276                         }
1277                 },
1278                 {
1279                         &hf_tlv_type,
1280                         {
1281                                 "Unknown TLV Type", "wmx.reg.unknown_tlv_type",
1282                                 FT_BYTES, BASE_NONE, NULL, 0x00, NULL, HFILL
1283                         }
1284                 },
1285                 {
1286                         &hf_reg_req_message_type,
1287                         {
1288                                 "MAC Management Message Type", "wmx.macmgtmsgtype.reg_req",
1289                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1290                         }
1291                 },
1292                 {
1293                         &hf_reg_invalid_tlv,
1294                         {
1295                                 "Invalid TLV", "wmx.reg_req.invalid_tlv",
1296                                 FT_BYTES, BASE_NONE, NULL, 0, NULL, HFILL
1297                         }
1298                 },
1299                 {
1300                         &hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame,
1301                         {
1302                                 "Maximum MAC level DL data per frame", "wmx.reg_req.max_mac_dl_data",
1303                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1304                         }
1305                 },
1306                 {
1307                         &hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame,
1308                         {
1309                                 "Maximum MAC level UL data per frame", "wmx.reg_req.max_mac_ul_data",
1310                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1311                         }
1312                 },
1313                 {
1314                         &hf_reg_req_min_time_for_inter_fa,
1315                         {
1316                                 "Minimum time for inter-FA HO, default=3", "wmx.reg_req.min_time_for_inter_fa",
1317                                 FT_UINT8, BASE_HEX, NULL, 0xF0, NULL, HFILL
1318                         }
1319                 },
1320                 {
1321                         &hf_reg_req_min_time_for_intra_fa,
1322                         {
1323                                 "Minimum time for intra-FA HO, default=2", "wmx.reg_req.min_time_for_intra_fa",
1324                                 FT_UINT8, BASE_HEX, NULL, 0x0F, NULL, HFILL
1325                         }
1326                 },
1327                 {
1328                         &hf_reg_req_tlv_t_45_ms_periodic_ranging_timer,
1329                         {
1330                                 "MS periodic ranging timer information", "wmx.reg_req.ms_periodic_ranging_timer_info",
1331                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1332                         }
1333                 },
1334                 {       /* IPv4 Mask */
1335                         &hf_ms_previous_ip_address_v4,
1336                         {
1337                                 "MS Previous IP address", "wmx.reg_req.ms_prev_ip_addr_v4",
1338                                 FT_IPv4, BASE_NONE, NULL, 0x0, NULL, HFILL
1339                         }
1340                 },
1341                 {       /* IPv6 Source Address */
1342                         &hf_ms_previous_ip_address_v6,
1343                         {
1344                                 "MS Previous IP address", "wmx.reg_req.ms_prev_ip_addr_v6",
1345                                 FT_IPv6, BASE_NONE, NULL, 0x0, NULL, HFILL
1346                         }
1347                 },
1348                 {
1349                         &hf_reg_req_secondary_mgmt_cid,
1350                         {
1351                                 "Secondary Management CID", "wmx.reg_req.secondary_mgmt_cid",
1352                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1353                         }
1354                 },
1355                 {
1356                         &hf_reg_req_tlv_t_32_sleep_mode_recovery_time,
1357                         {
1358                                 "Frames required for the MS to switch from sleep to awake-mode", "wmx.reg_req.sleep_recovery",
1359                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1360                         }
1361                 },
1362                 {
1363                         &hf_reg_power_saving_class_type_i,
1364                         {
1365                                 "Power saving class type I supported", "wmx.reg.power_saving_class_type_i",
1366                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
1367                         }
1368                 },
1369                 {
1370                         &hf_reg_power_saving_class_type_ii,
1371                         {
1372                                 "Power saving class type II supported", "wmx.reg.power_saving_class_type_ii",
1373                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
1374                         }
1375                 },
1376                 {
1377                         &hf_reg_power_saving_class_type_iii,
1378                         {
1379                                 "Power saving class type III supported", "wmx.reg.power_saving_class_type_iii",
1380                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
1381                         }
1382                 },
1383                 {
1384                         &hf_reg_multi_active_power_saving_classes,
1385                         {
1386                                 "Multiple active power saving classes supported", "wmx.reg.multi_active_power_saving_classes",
1387                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, NULL, HFILL
1388                         }
1389                 },
1390                 {
1391                         &hf_reg_total_power_saving_class_instances,
1392                         {
1393                                 "Total number of power saving class instances of all", "wmx.reg_req.total_power_saving_class_instances",
1394                                 FT_UINT16, BASE_DEC, NULL, 0x1F0, NULL, HFILL
1395                         }
1396                 },
1397                 {
1398                         &hf_reg_power_saving_class_reserved,
1399                         {
1400                                 "Reserved", "wmx.reg.reserved",
1401                                 FT_UINT16, BASE_DEC, NULL, 0xFE00, NULL, HFILL
1402                         }
1403                 }
1404         };
1405
1406         /* Setup protocol subtree array */
1407         static gint *ett[] =
1408                 {
1409                         &ett_mac_mgmt_msg_reg_req_decoder
1410                 };
1411
1412
1413         proto_mac_mgmt_msg_reg_req_decoder = proto_register_protocol (
1414                 "WiMax REG-REQ/RSP Messages", /* name       */
1415                 "WiMax REG-REQ/RSP (reg)",    /* short name */
1416                 "wmx.reg"                     /* abbrev     */
1417                 );
1418
1419         proto_register_field_array(proto_mac_mgmt_msg_reg_req_decoder, hf, array_length(hf));
1420         proto_register_subtree_array(ett, array_length(ett));
1421 }