sfrench/cifs-2.6.git
8 months agoRevert "drm/amd/display: Hande writeback request from userspace"
Alex Hung [Wed, 11 Oct 2023 19:18:46 +0000 (13:18 -0600)]
Revert "drm/amd/display: Hande writeback request from userspace"

This reverts commit cd1a4bc22821eea9a98f1beddd1a8d789989a720.

[WHY & HOW]
The writeback series cause a regression in thunderbolt display.

Signed-off-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agoRevert "drm/amd/display: Add writeback enable/disable in dc"
Alex Hung [Wed, 11 Oct 2023 19:18:45 +0000 (13:18 -0600)]
Revert "drm/amd/display: Add writeback enable/disable in dc"

This reverts commit c6d3c7b6309726fbe93cf595d6de326fb8295a64.

[WHY & HOW]
The writeback series cause a regression in thunderbolt display.

Signed-off-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agoRevert "drm/amd/display: Fix writeback_info never got updated"
Alex Hung [Wed, 11 Oct 2023 19:18:44 +0000 (13:18 -0600)]
Revert "drm/amd/display: Fix writeback_info never got updated"

This reverts commit 8a307777c36e15f38c9f23778babcd368144c7d8.

[WHY & HOW]
The writeback series cause a regression in thunderbolt display.

Signed-off-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agoRevert "drm/amd/display: Validate hw_points_num before using it"
Alex Hung [Wed, 11 Oct 2023 19:18:38 +0000 (13:18 -0600)]
Revert "drm/amd/display: Validate hw_points_num before using it"

This reverts commit 58c3b3341cea4f75dc8c003b89f8a6dd8ec55e50.

[WHY & HOW]
The writeback series cause a regression in thunderbolt display.

Signed-off-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agoRevert "drm/amd/display: Fix writeback_info is not removed"
Alex Hung [Wed, 11 Oct 2023 19:18:36 +0000 (13:18 -0600)]
Revert "drm/amd/display: Fix writeback_info is not removed"

This reverts commit 5b89d2ccc8466e0445a4994cb288fc009b565de5.

[WHY & HOW]
The writeback series cause a regression in thunderbolt display.

Signed-off-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agoRevert "drm/amd/display: Add writeback enable field (wb_enabled)"
Alex Hung [Wed, 11 Oct 2023 19:18:34 +0000 (13:18 -0600)]
Revert "drm/amd/display: Add writeback enable field (wb_enabled)"

This reverts commit f6893fcb10c7b24526454e465f6ec2563ef044cc.

[WHY & HOW]
The writeback series cause a regression in thunderbolt display.

Signed-off-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agoRevert "drm/amd/display: Setup for mmhubbub3_warmup_mcif with big buffer"
Alex Hung [Wed, 11 Oct 2023 19:18:33 +0000 (13:18 -0600)]
Revert "drm/amd/display: Setup for mmhubbub3_warmup_mcif with big buffer"

This reverts commit 428542d9177286c01ef7a3dbd026eb00567e06b1.

[WHY & HOW]
The writeback series cause a regression in thunderbolt display.

Signed-off-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agoRevert "drm/amd/display: Add new set_fc_enable to struct dwbc_funcs"
Alex Hung [Wed, 11 Oct 2023 19:18:31 +0000 (13:18 -0600)]
Revert "drm/amd/display: Add new set_fc_enable to struct dwbc_funcs"

This reverts commit b79a00a4d4f8fc827ca0fc19e259913a81252f6b.

[WHY & HOW]
The writeback series cause a regression in thunderbolt display.

Signed-off-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agoRevert "drm/amd/display: Disable DWB frame capture to emulate oneshot"
Alex Hung [Wed, 11 Oct 2023 19:18:24 +0000 (13:18 -0600)]
Revert "drm/amd/display: Disable DWB frame capture to emulate oneshot"

This reverts commit 77a66faaccc0455fe30e326e9a997aec8d0abed4.

[WHY & HOW]
The writeback series cause a regression in thunderbolt display.

Signed-off-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Revert "drm/amd/display: Use drm_connector in create_validate_stream...
Alex Hung [Tue, 10 Oct 2023 22:39:32 +0000 (16:39 -0600)]
drm/amd/display: Revert "drm/amd/display: Use drm_connector in create_validate_stream_for_sink"

This reverts commit c4c182b5488e8d4a48be3327aab14d778cdfe5e7.

After this was commit PCON and USB4 issues were observed. A new fix will
be submitted instead.

Signed-off-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Expose ras version & schema info
Asad Kamal [Mon, 2 Oct 2023 06:41:00 +0000 (14:41 +0800)]
drm/amdgpu: Expose ras version & schema info

Expose ras table version & schema info to sysfs

v2: Updated schema to get poison support info
from ras context, removed asic specific checks

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Read PSPv13 OS version from register
Lijo Lazar [Tue, 10 Oct 2023 07:19:25 +0000 (12:49 +0530)]
drm/amdgpu: Read PSPv13 OS version from register

PSP OS updates the version information in register. On APUs with PSPv13,
PSP OS will already be loaded with SBIOS. Hence use the version register
instead of using information in driver binary header.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: add missing NULL check for DML2
Bob Zhou [Tue, 10 Oct 2023 03:02:44 +0000 (11:02 +0800)]
drm/amd/display: add missing NULL check for DML2

Recently, the driver introduce DML2 for future ASIC support.
But, some ASIC's hubbub pointer is null before calling.
It cause the below null pointer issue, so add null check to fix it.

BUG: kernel NULL pointer dereference, address: 0000000000000000
RIP: 0010:dc_create_resource_pool+0xc1/0x2c0 [amdgpu] Call Trace:
 <TASK>
 ? show_regs.cold+0x1a/0x1f
 ? __die_body+0x20/0x70
 ? __die+0x2b/0x37
 ? page_fault_oops+0x136/0x2c0
 ? do_user_addr_fault+0x303/0x660
 ? exc_page_fault+0x77/0x170
 ? asm_exc_page_fault+0x27/0x30
 ? dc_create_resource_pool+0xc1/0x2c0 [amdgpu]  ? dc_create_resource_pool+0x243/0x2c0 [amdgpu]
 dc_create+0x23f/0x6b0 [amdgpu]
 ? dmi_matches+0xa3/0x200
 amdgpu_dm_init+0x2bd/0x22a0 [amdgpu]

Fixes: 7966f319c66d ("drm/amd/display: Introduce DML2")
Signed-off-by: Bob Zhou <bob.zhou@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu/umsch: enable doorbell for umsch
Lang Yu [Sun, 1 Oct 2023 16:10:42 +0000 (00:10 +0800)]
drm/amdgpu/umsch: enable doorbell for umsch

Program vcn_doorbell_range with vcn_ring0_1.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: make dc_set_power_state() return type `void` again
Mario Limonciello [Fri, 6 Oct 2023 18:50:26 +0000 (13:50 -0500)]
drm/amd/display: make dc_set_power_state() return type `void` again

As dc_set_power_state() no longer allocates memory, it's not necessary
to have return types and check return code as it can't fail anymore.

Change it back to `void`.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Destroy DC context while keeping DML and DML2
Mario Limonciello [Fri, 6 Oct 2023 18:50:25 +0000 (13:50 -0500)]
drm/amd/display: Destroy DC context while keeping DML and DML2

If there is memory pressure at suspend time then dynamically
allocating a large structure as part of DC suspend code will
fail.

Instead re-use the same structures and clear all members except
those that should be maintained.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2362
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Catch errors from drm_atomic_helper_suspend()
Mario Limonciello [Fri, 6 Oct 2023 18:50:24 +0000 (13:50 -0500)]
drm/amd/display: Catch errors from drm_atomic_helper_suspend()

drm_atomic_helper_suspend() can return PTR_ERR(), in which case the
error gets stored into `dm->cached_state`.  This can cause failures
during resume.  Catch the error during suspend and fail the suspend
instead.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2362
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd: Split up UVD suspend into prepare and suspend steps
Mario Limonciello [Fri, 6 Oct 2023 18:50:22 +0000 (13:50 -0500)]
drm/amd: Split up UVD suspend into prepare and suspend steps

amdgpu_uvd_suspend() allocates memory and copies objects into that
allocated memory.  This fails under memory pressure.  Instead move
majority of this code into a prepare step when swap can still be
allocated.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd: Add concept of running prepare_suspend() sequence for IP blocks
Mario Limonciello [Fri, 6 Oct 2023 18:50:21 +0000 (13:50 -0500)]
drm/amd: Add concept of running prepare_suspend() sequence for IP blocks

If any IP blocks allocate memory during their hw_fini() sequence
this can cause the suspend to fail under memory pressure.  Introduce
a new phase that IP blocks can use to allocate memory before suspend
starts so that it can potentially be evicted into swap instead.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd: Evict resources during PM ops prepare() callback
Mario Limonciello [Fri, 6 Oct 2023 18:50:20 +0000 (13:50 -0500)]
drm/amd: Evict resources during PM ops prepare() callback

Linux PM core has a prepare() callback run before suspend.

If the system is under high memory pressure, the resources may need
to be evicted into swap instead.  If the storage backing for swap
is offlined during the suspend() step then such a call may fail.

So move this step into prepare() to move evict majority of
resources and update all non-pmops callers to call the same callback.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2362
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: enable GFX IP v11.5.0 CG and PG support
Li Ma [Wed, 2 Aug 2023 08:39:51 +0000 (16:39 +0800)]
drm/amdgpu: enable GFX IP v11.5.0 CG and PG support

Add CG support for GFX/MC/HDP/ATHUB/IH/BIF.
Add PG support for GFX.

Signed-off-by: Li Ma <li.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: add support to power up/down UMSCH by SMU
Lang Yu [Fri, 2 Jun 2023 00:39:36 +0000 (08:39 +0800)]
drm/amdgpu: add support to power up/down UMSCH by SMU

Power up/down UMSCH by SMU.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: add power up/down UMSCH ppt callback
Lang Yu [Fri, 2 Jun 2023 00:36:28 +0000 (08:36 +0800)]
drm/amdgpu: add power up/down UMSCH ppt callback

Add ppt callback to power up/down UMSCH.

v2: squash in updates (Alex)

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: add support to powerup VPE by SMU
Lang Yu [Wed, 17 May 2023 06:55:46 +0000 (14:55 +0800)]
drm/amdgpu: add support to powerup VPE by SMU

Powerup VPE by SMU.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu/discovery: add SMU 14 support
Li Ma [Fri, 28 Apr 2023 06:08:14 +0000 (14:08 +0800)]
drm/amdgpu/discovery: add SMU 14 support

add smu 14 into the IP discovery list.

Signed-off-by: Li Ma <li.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/swsmu: add smu14 ip support
Kenneth Feng [Wed, 26 Apr 2023 06:02:25 +0000 (14:02 +0800)]
drm/amd/swsmu: add smu14 ip support

Add initial swSMU support for smu 14 series ASIC.

v2: squash in build fixes and updates (Li Ma)
    fix warnings (Alex)
v3: squash in updates (Alex)
v4: squash in updates (Alex)
v5: squash in avg/current power updates (Alex)

Signed-off-by: Li Ma <li.ma@amd.com>
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/swsmu: add smu v14_0_0 pmfw if file
Li Ma [Fri, 28 Apr 2023 05:52:04 +0000 (13:52 +0800)]
drm/amd/swsmu: add smu v14_0_0 pmfw if file

Add initial smu v14_0_0 pmfw if file

v2: squash in updates (Alex)

Signed-off-by: Li Ma <li.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/swsmu: add smu v14_0_0 ppsmc file
Li Ma [Fri, 28 Apr 2023 05:22:06 +0000 (13:22 +0800)]
drm/amd/swsmu: add smu v14_0_0 ppsmc file

Add initial smu v14_0_0 ppsmc file

v2: squash in updates (Alex)
v3: squash in updates (Alex)

Signed-off-by: Li Ma <li.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu/swsmu: add smu v14_0_0 driver if file
Li Ma [Fri, 28 Apr 2023 07:33:12 +0000 (15:33 +0800)]
drm/amdgpu/swsmu: add smu v14_0_0 driver if file

Add initial smu v14_0_0 driver if file

v2: squash in updates (Alex)
v3: update interface (Alex)

Signed-off-by: Li Ma <li.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu/umsch: power on/off UMSCH by DLDO
Lang Yu [Sat, 30 Sep 2023 06:39:26 +0000 (14:39 +0800)]
drm/amdgpu/umsch: power on/off UMSCH by DLDO

VCN 4.0.5 uses DLDO.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu/umsch: fix psp frontdoor loading
Lang Yu [Sat, 7 Oct 2023 04:43:13 +0000 (12:43 +0800)]
drm/amdgpu/umsch: fix psp frontdoor loading

These changes are missed in rebase.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Increase IP discovery region size
Lijo Lazar [Fri, 6 Oct 2023 04:57:20 +0000 (10:27 +0530)]
drm/amdgpu: Increase IP discovery region size

IP discovery region has increased to > 8K on some SOCs.Maximum reserve
size is upto 12K, but not used. For now increase to 10K.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/pm: Use gpu_metrics_v1_4 for SMUv13.0.6
Asad Kamal [Wed, 27 Sep 2023 13:08:13 +0000 (21:08 +0800)]
drm/amd/pm: Use gpu_metrics_v1_4 for SMUv13.0.6

Use gpu_metrics_v1_4 for SMUv13.0.6 to fill
gpu metric info

v3: Removed filling gpu metric instantaneous
pcie bw

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/pm: Add gpu_metrics_v1_4
Asad Kamal [Wed, 27 Sep 2023 13:05:37 +0000 (21:05 +0800)]
drm/amd/pm: Add gpu_metrics_v1_4

Add new gpu_metrics_v1_4 to acquire XGMI data transfer,
pcie bandwidth & Clock lock status

v2:
Add pcie error counter to gpu metric table v1_4

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/pm: Update metric table for smu v13_0_6
Asad Kamal [Wed, 4 Oct 2023 06:04:57 +0000 (14:04 +0800)]
drm/amd/pm: Update metric table for smu v13_0_6

Update pmfw metric table to include xgmi transfer
data and pci instantaneous bandwidth for smu v13_0_6

v2:
Updated metric table version

v3: Removed inst pcie bw with alignment to metrics table
version 8

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Return -EINVAL when MMSCH init status incorrect
Lin.Cao [Sun, 8 Oct 2023 09:36:40 +0000 (17:36 +0800)]
drm/amdgpu: Return -EINVAL when MMSCH init status incorrect

Return -EINVAL when MMSCH init fail which can be handle by function
amdgpu_device_reset_sriov correctly.

Signed-off-by: Lin.Cao <lincao12@amd.com>
Reviewed-by: Jingwen Chen <Jingwen.Chen2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/pm: wait for completion of the EnableGfxImu command
Tim Huang [Mon, 9 Oct 2023 08:23:27 +0000 (16:23 +0800)]
drm/amd/pm: wait for completion of the EnableGfxImu command

Wait for completion of sending the EnableGfxImu message
when using the PSP FW loading.

Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu/vpe: fix insert_nop ops
Lang Yu [Sat, 7 Oct 2023 02:13:49 +0000 (10:13 +0800)]
drm/amdgpu/vpe: fix insert_nop ops

Avoid infinite loop when count is 0.
This is missed in rebase.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Address member 'gart_placement' not described in 'amdgpu_gmc_gart_location'
Srinivasan Shanmugam [Mon, 9 Oct 2023 14:53:32 +0000 (20:23 +0530)]
drm/amdgpu: Address member 'gart_placement' not described in 'amdgpu_gmc_gart_location'

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:274: warning: Function parameter or member 'gart_placement' not described in 'amdgpu_gmc_gart_location'

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu/vpe: align with mcbp changes
Lang Yu [Sat, 7 Oct 2023 02:10:50 +0000 (10:10 +0800)]
drm/amdgpu/vpe: align with mcbp changes

MCBP is decided by adev->gfx.mcbp now.
This is missed in rebase.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu/vpe: remove IB end boundary requirement
Lang Yu [Fri, 6 Oct 2023 12:24:45 +0000 (20:24 +0800)]
drm/amdgpu/vpe: remove IB end boundary requirement

Remove IB end boundary requirement,
VPE has no such limitions, use existing
amdgpu_ring_generic_pad_ib() instead.
This is missed in rebase.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Improve MES responsiveness during oversubscription
Jay Cornwall [Wed, 4 Oct 2023 15:53:26 +0000 (10:53 -0500)]
drm/amdgpu: Improve MES responsiveness during oversubscription

When MES is oversubscribed it may not frequently check for new
command submissions from driver if the scheduling load is high.
Response latency as high as 5 seconds has been observed.

Enable a flag which adds a check for new commands between
scheduling quantums.

Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Cc: Alexandru Tudor <alexandru.tudor@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: fix SI failure due to doorbells allocation
Icenowy Zheng [Sun, 8 Oct 2023 06:46:49 +0000 (14:46 +0800)]
drm/amdgpu: fix SI failure due to doorbells allocation

SI hardware does not have doorbells at all, however currently the code
will try to do the allocation and thus fail, makes SI AMDGPU not usable.

Fix this failure by skipping doorbells allocation when doorbells count
is zero.

Fixes: 54c30d2a8def ("drm/amdgpu: create kernel doorbell pages")
Reviewed-by: Shashank Sharma <shashank.sharma@amd.com>
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu/discovery: enable DCN 3.5.0 support
Aaron Liu [Thu, 25 May 2023 08:08:55 +0000 (16:08 +0800)]
drm/amdgpu/discovery: enable DCN 3.5.0 support

Enable DCN 3.5.0 support.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdkfd: get doorbell's absolute offset based on the db_size
Arvind Yadav [Mon, 9 Oct 2023 17:13:16 +0000 (22:43 +0530)]
drm/amdkfd: get doorbell's absolute offset based on the db_size

Here, Adding db_size in byte to find the doorbell's
absolute offset for both 32-bit and 64-bit doorbell sizes.
So that doorbell offset will be aligned based on the doorbell
size.

v2:
- Addressed the review comment from Felix.
v3:
- Adding doorbell_size as parameter to get db absolute offset.
v4:
  Squash the two patches into one.

Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
Signed-off-by: Arvind Yadav <Arvind.Yadav@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: add missing NULL check
Christian König [Fri, 6 Oct 2023 12:04:04 +0000 (14:04 +0200)]
drm/amdgpu: add missing NULL check

bo->tbo.resource can easily be NULL here.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2902
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CC: stable@vger.kernel.org
8 months agodrm/amd/display: 3.2.255
Aric Cyr [Mon, 2 Oct 2023 00:40:08 +0000 (20:40 -0400)]
drm/amd/display: 3.2.255

This version brings along following fixes:
- Refactor DPG test pattern logic for ODM cases
- Refactor HWSS into component folder
- Revert "drm/amd/display: Add a check for idle power optimization"
- Revert "drm/amd/display: remove duplicated edp relink to fastboot
- Update cursor limits based on SW cursor fallback limits
- Update stream mask
- Update pmfw_driver_if new structure
- Modify SMU message logs
- Don't set dpms_off for seamless boot

Known issue:
DWB (Writeback functionality) is broken.
Fix will be available in DC 3.2.256

Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Disable virtual links
Stylon Wang [Thu, 5 Oct 2023 12:25:10 +0000 (20:25 +0800)]
drm/amd/display: Disable virtual links

[Why]
This could work around the issue with DP tunneling producing
a NULL pointer dereference.

[How]
Disable the virtual links.

Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Disable SubVP if test pattern is enabled
George Shen [Fri, 22 Sep 2023 18:38:31 +0000 (14:38 -0400)]
drm/amd/display: Disable SubVP if test pattern is enabled

[Why]
Enabling DPG causes HUBP to stay in blank constantly. If DPG is enabled
while an MCLK switch is taking place with SubVP, it will cause the MCLK
to never complete. This is because SubVP MCLK switch relies a HUBP
VLine interrupt, which will never occur when HUBP is constantly in
blank.

[How]
Disable SubVP when test pattern is enabled.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Refactor DPG test pattern logic for ODM cases
George Shen [Fri, 22 Sep 2023 18:26:39 +0000 (14:26 -0400)]
drm/amd/display: Refactor DPG test pattern logic for ODM cases

[Why]
Current DPG test pattern logic does not account for ODM configuration
changes after test pattern has already been programmed. For example, if
ODM2:1 is enabled after test pattern is already being output, the second
pipe is not programmed to output test pattern, causing half the screen
to be black.

[How]
Move DPG test pattern parameter calculations into separate function.
Whenever ODM pipe configuration changes, re-calculate DPG test pattern
parameters and program DPG if test pattern is currently enabled.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Don't set dpms_off for seamless boot
Daniel Miess [Fri, 29 Sep 2023 17:04:33 +0000 (13:04 -0400)]
drm/amd/display: Don't set dpms_off for seamless boot

[Why]
eDPs fail to light up with seamless boot enabled

[How]
When seamless boot is enabled don't configure dpms_off
in disable_vbios_mode_if_required.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Refactor HWSS into component folder
Mounika Adhuri [Fri, 22 Sep 2023 12:53:28 +0000 (18:23 +0530)]
drm/amd/display: Refactor HWSS into component folder

[why]
Rename hw_sequencer to hwseq.
Move all hwseq files to unique
folder hwss.

[how]
creating hwss repo in dc, and moved the dcnxx_hwseq.c
and .h files into corresponding new folders inside the hwss
and cleared the linkage errors by adding relative paths
in the Makefile.template.

Reviewed-by: Martin Leung <martin.leung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Mounika Adhuri <moadhuri@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Revert "drm/amd/display: Add a check for idle power optimization"
Sung Joon Kim [Thu, 28 Sep 2023 15:20:13 +0000 (11:20 -0400)]
drm/amd/display: Revert "drm/amd/display: Add a check for idle power optimization"

Revert commit 434cf7af492f ("drm/amd/display: Add a check for idle power optimization")
Because it cause Freesync and S4 regression

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: add hub->ctx_distance in setup_vmid_config
Yifan Zhang [Thu, 28 Sep 2023 06:02:02 +0000 (14:02 +0800)]
drm/amdgpu: add hub->ctx_distance in setup_vmid_config

add hub->ctx_distance when read CONTEXT1_CNTL, align w/
write back operation.

v2: fix coding style errors reported by checkpatch.pl (Christian)

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Lang Yu <lang.yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Don't use fsleep for PSR exit waits
Nicholas Kazlauskas [Wed, 27 Sep 2023 19:06:41 +0000 (15:06 -0400)]
drm/amd/display: Don't use fsleep for PSR exit waits

[Why]
These functions can be called from high IRQ levels and the OS will hang
if it tries to use a usleep_highres or a msleep.

[How]
Replace the fsleep with a udelay.

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Update cursor limits based on SW cursor fallback limits
Alvin Lee [Wed, 27 Sep 2023 22:39:31 +0000 (18:39 -0400)]
drm/amd/display: Update cursor limits based on SW cursor fallback limits

[Why&How]
For determining the cursor size limit, use the same checks that
are used for determining SW cursor fallback instead of only
using SubVP

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Update dml ssb from pmfw clock table
Muhammad Ahmed [Tue, 26 Sep 2023 19:46:21 +0000 (15:46 -0400)]
drm/amd/display: Update dml ssb from pmfw clock table

[why]
Need to use real clock table

[How]
Update the clock table

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Update stream mask
Duncan Ma [Wed, 27 Sep 2023 19:17:27 +0000 (15:17 -0400)]
drm/amd/display: Update stream mask

[Why]
Whenever stream changes because of new
pipe arrangements such as ODM. The new
stream mask is not reflected in DMCUB.

The mismatch in stream mask is blocking ips
entry in some scenarios.

[How]
Whenever stream arrangement changes,
update stream mask and notify DMCUB.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Revert "drm/amd/display: remove duplicated edp relink to fastboot"
Aric Cyr [Tue, 26 Sep 2023 20:15:37 +0000 (16:15 -0400)]
drm/amd/display: Revert "drm/amd/display: remove duplicated edp relink to fastboot"

Revert commit 984abb5384b0 ("drm/amd/display: remove duplicated edp relink to fastboot")

Because it cause 4k EDP not light up on boot

Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Modify Vmin default value
Max Tseng [Fri, 22 Sep 2023 08:50:53 +0000 (16:50 +0800)]
drm/amd/display: Modify Vmin default value

Fine tune the Vmin clock value

Reviewed-by: Robin Chen <robin.chen@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Max Tseng <max.tseng@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Update pmfw_driver_if new structure
Charlene Liu [Tue, 26 Sep 2023 19:32:59 +0000 (15:32 -0400)]
drm/amd/display: Update pmfw_driver_if new structure

[why]
pmfw header file updated, need align with data structure.

[How]
Update the data structure.

Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: VSIF v3 set Max Refresh Rate
Muhammad Ansari [Mon, 25 Sep 2023 16:00:31 +0000 (12:00 -0400)]
drm/amd/display: VSIF v3 set Max Refresh Rate

[WHY]
FreeSync spec requires PB8 and PB12 to be set to nominal
refresh rate regardless of fixed rate or variable

[HOW]
Removed the condition that checks and overwrites max refresh rate
and set PB8/PB12 to be set to max refresh rate always

Reviewed-by: Anthony Koo <anthony.koo@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Muhammad Ansari <muhammad.ansari@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Modify SMU message logs
Sung Joon Kim [Tue, 19 Sep 2023 21:04:59 +0000 (17:04 -0400)]
drm/amd/display: Modify SMU message logs

[why]
It's important to make sure SMU messages
are logged by default to improve debugging for
power optimization use cases.

[how]
Change logs to warnings when SMU message
returns non-success id.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Fix potential null pointer derefernce
Stanley.Yang [Wed, 27 Sep 2023 08:22:29 +0000 (16:22 +0800)]
drm/amdgpu: Fix potential null pointer derefernce

The amdgpu_ras_get_context may return NULL if device
not support ras feature, so add check before using.

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: enable S/G display for for recent APUs by default
Yifan Zhang [Wed, 27 Sep 2023 04:56:15 +0000 (12:56 +0800)]
drm/amd/display: enable S/G display for for recent APUs by default

With S/G display becomes stable, enable S/G display for recent APUs
by default rather than white list.

v2: explicitly disable sg on pre-CZ chips (Alex)
v3: add parens for every clause (Alex)

Co-authored-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agoDocumentation/amdgpu: Add FRU attribute details
Lijo Lazar [Wed, 4 Oct 2023 13:16:06 +0000 (18:46 +0530)]
Documentation/amdgpu: Add FRU attribute details

Add documentation for the newly added manufacturer and fru_id attributes
in sysfs.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Add more FRU field information
Lijo Lazar [Wed, 4 Oct 2023 13:02:02 +0000 (18:32 +0530)]
drm/amdgpu: Add more FRU field information

Add support to read Manufacturer Name and FRU File Id fields. Also add
sysfs device attributes for external usage.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Refactor FRU product information
Lijo Lazar [Wed, 4 Oct 2023 10:30:47 +0000 (16:00 +0530)]
drm/amdgpu: Refactor FRU product information

Keep FRU related information together in a separate structure.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: enable FRU device for SMU v13.0.6
Yang Wang [Thu, 21 Sep 2023 07:25:43 +0000 (15:25 +0800)]
drm/amdgpu: enable FRU device for SMU v13.0.6

v1:
enable GFX v9.4.3 FRU device to query board information.

v2:
use MP1 version to identify different asic

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: update ib start and size alignment
Boyuan Zhang [Fri, 6 Oct 2023 02:09:08 +0000 (22:09 -0400)]
drm/amdgpu: update ib start and size alignment

Update IB starting address alignment and size alignment with correct values
for decode and encode IPs.

Decode IB starting address alignment: 256 bytes
Decode IB size alignment: 64 bytes
Encode IB starting address alignment: 256 bytes
Encode IB size alignment: 4 bytes

Also bump amdgpu driver version for this update.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: add check in validate_only in dml2
Gabe Teeger [Thu, 28 Sep 2023 21:00:35 +0000 (17:00 -0400)]
drm/amd/display: add check in validate_only in dml2

[what]
does_configuration_meet_sw_policies check was not done in the
validate_only portion of dml2, so some unsupported modes were passing bw
validation, only to fail the same check later in validate_and_build. now
we add the check to validate_only.

Also add line in dcn35_resource to ensure that value set for
enable_windowed_mpo_odm gets passed to dml.

[why]
Immediate black screen during video playback at 4k144hz. The debugger
showed that we were failing validation in dml on every updateplanes().

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Port replay vblank logic to DML2
Daniel Miess [Wed, 27 Sep 2023 19:21:53 +0000 (15:21 -0400)]
drm/amd/display: Port replay vblank logic to DML2

Update DML2 with replay vblank logic found in DML1.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Modify Pipe Selection for Policy for ODM
Saaem Rizvi [Mon, 25 Sep 2023 04:45:25 +0000 (00:45 -0400)]
drm/amd/display: Modify Pipe Selection for Policy for ODM

[Why]
There are certain cases during a transition to ODM that might cause
corruption on the display. This occurs when we choose certain pipes in a
particular state.

[How]
We now will store the pipe indexes of the any pipes that might be
problematic to switch to during an ODM transition, and only use them as
a last resort.

Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Saaem Rizvi <syedsaaem.rizvi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: correct dml2 input and dlg_refclk
Charlene Liu [Wed, 30 Aug 2023 01:08:38 +0000 (21:08 -0400)]
drm/amd/display: correct dml2 input and dlg_refclk

dc->dml2_options.use_native_pstate_optimization flag will make driver
use dcn32 legacy_svp_drr related tuning. Set this to false fixed the
stutter underflow issue also based on HW suggest disable ODM by default
and let DML choose it.

Reviewed-by: Zhan Liu <zhan.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Fix Chroma Surface height/width initialization
Sung Joon Kim [Thu, 17 Aug 2023 16:21:55 +0000 (12:21 -0400)]
drm/amd/display: Fix Chroma Surface height/width initialization

[why]
Surface height/width for Chroma has another variable that it should be
intialized to, chroma_size. Fixing this will help pass DML2.0 validation
for YCbCr420 tests, DCHB006.109,129, DCHB014.011,012.

[how]
Assign SurfaceHeight/WidthC to chroma_size.height/width

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Move stereo timing check to helper
Taimur Hassan [Wed, 16 Aug 2023 21:13:10 +0000 (17:13 -0400)]
drm/amd/display: Move stereo timing check to helper

Rework dml2_map_dc_pipes to keep the logic clean.

Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Split pipe for stereo timings
Taimur Hassan [Tue, 25 Jul 2023 21:10:37 +0000 (17:10 -0400)]
drm/amd/display: Split pipe for stereo timings

[Why & How]
DML2 did not carry over DML1 logic that splits pipe for stero timings. Pipe
splitting is needed in this case to pass stereo tests.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Use fixed DET Buffer Size
Sung Joon Kim [Wed, 9 Aug 2023 20:39:53 +0000 (16:39 -0400)]
drm/amd/display: Use fixed DET Buffer Size

[why]
Regression from DML1.0 where we use differen DET buffer sizes for each
pipe. From the spec, we need to use DET buffer size of 384 kb for each
pipe

[how]
Ensure to use 384 kb DET buffer sizes for each available pipe.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Handle multiple streams sourcing same surface
Sung Joon Kim [Wed, 9 Aug 2023 20:09:28 +0000 (16:09 -0400)]
drm/amd/display: Handle multiple streams sourcing same surface

[why]
There are cases where more than 1 stream can be mapped to the same
surface. DML2.0 does not seem to handle these cases.

[how]
Make sure to account for the stream id when deriving the plane id. By
doing this, each plane id will be unique based on the stream id.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Add z8_marks in dml
Charlene Liu [Tue, 1 Aug 2023 00:01:11 +0000 (20:01 -0400)]
drm/amd/display: Add z8_marks in dml

Add z8 watermarks to struct for later ASIC use.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Add DCN35 DML2 support
Qingqing Zhuo [Thu, 3 Aug 2023 04:43:25 +0000 (00:43 -0400)]
drm/amd/display: Add DCN35 DML2 support

Enable DML2 for DCN35.

Changes since V1:
- Remove hard coded values

Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Introduce DML2
Qingqing Zhuo [Fri, 28 Jul 2023 21:55:30 +0000 (17:55 -0400)]
drm/amd/display: Introduce DML2

DC is transitioning from DML to DML2, and this commit introduces all the
required changes for some of the already available ASICs and adds the
required code infra to support new ASICs under DML2. DML2 is also a
generated code that provides better mode verification and programming
models for software/hardware, and it enables a better way to create
validation tools. This version is more like a middle step to the
complete transition to the DML2 version.

Changes since V1:
- Alex: Fix typos

Changes since V2:
- Update DC includes

Changes since V3:
- Fix 32 bit compilation issues on x86

Changes since V4:
- Avoid compilation of DML2 on some not supported 32-bit architecture
- Update commit message

Co-developed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Co-developed-by: Roman Li <roman.li@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Move dml code under CONFIG_DRM_AMD_DC_FP guard
Rodrigo Siqueira [Tue, 3 Oct 2023 01:44:55 +0000 (19:44 -0600)]
drm/amd/display: Move dml code under CONFIG_DRM_AMD_DC_FP guard

For some reason, the dml code is not guarded under CONFIG_DRM_AMD_DC_FP
in the Makefile. This commit moves the dml code under the DC_FP guard.

Reviewed-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Move bw_fixed from DML folder
Rodrigo Siqueira [Tue, 3 Oct 2023 14:14:49 +0000 (08:14 -0600)]
drm/amd/display: Move bw_fixed from DML folder

bw_fixed does not need any FPU operation, and it is used on DCE and DCN.
For this reason, this commit moves bw_fixed to the basic folder outside
DML.

Reviewed-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Move custom_float from DML folder
Rodrigo Siqueira [Tue, 3 Oct 2023 14:05:56 +0000 (08:05 -0600)]
drm/amd/display: Move custom_float from DML folder

The custom_float file does not have any FPU operation, so it should be
inside DML. This commit moves the file to the basic folder.

Reviewed-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Move dce_calcs from DML folder
Rodrigo Siqueira [Tue, 3 Oct 2023 14:24:28 +0000 (08:24 -0600)]
drm/amd/display: Move dce_calcs from DML folder

dce_calcs does not have FPU operations, and it is required for DCE and
DCN. Remove this file from the DML folder and add it to the basic folder
visible for DCE and DCN.

Reviewed-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Enable SMU 13.0.0 optimizations when ROCm is active (v2)
Alex Deucher [Fri, 11 Aug 2023 02:54:52 +0000 (10:54 +0800)]
drm/amdgpu: Enable SMU 13.0.0 optimizations when ROCm is active (v2)

When ROCm is active enable additional SMU 13.0.0 optimizations.
This reuses the unused powersave profile on PMFW.

v2: move to the swsmu code since we need both bits active in
    the workload mask.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Move the memory allocation out of dcn20_validate_bandwidth_fp().
Sebastian Andrzej Siewior [Thu, 21 Sep 2023 14:15:16 +0000 (16:15 +0200)]
drm/amd/display: Move the memory allocation out of dcn20_validate_bandwidth_fp().

dcn20_validate_bandwidth_fp() is invoked while FPU access has been
enabled. FPU access requires disabling preemption even on PREEMPT_RT.
It is not possible to allocate memory with disabled preemption even with
GFP_ATOMIC on PREEMPT_RT.

Move the memory allocation before FPU access is enabled.
To preserve previous "clean" state of "pipes" add a memset() before the
second invocation of dcn20_validate_bandwidth_internal() where the
variable is used.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Move the memory allocation out of dcn21_validate_bandwidth_fp().
Sebastian Andrzej Siewior [Thu, 21 Sep 2023 14:15:15 +0000 (16:15 +0200)]
drm/amd/display: Move the memory allocation out of dcn21_validate_bandwidth_fp().

dcn21_validate_bandwidth_fp() is invoked while FPU access has been
enabled. FPU access requires disabling preemption even on PREEMPT_RT.
It is not possible to allocate memory with disabled preemption even with
GFP_ATOMIC on PREEMPT_RT.

Move the memory allocation before FPU access is enabled.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=217928
Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd/display: Add a warning if the FPU is used outside from task context.
Sebastian Andrzej Siewior [Thu, 21 Sep 2023 14:15:14 +0000 (16:15 +0200)]
drm/amd/display: Add a warning if the FPU is used outside from task context.

Add a warning if the FPU is used from any context other than task
context. This is only precaution since the code is not able to be used
from softirq while the API allows it on x86 for instance.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd: Fix UBSAN array-index-out-of-bounds for Polaris and Tonga
Mario Limonciello [Wed, 4 Oct 2023 20:46:44 +0000 (15:46 -0500)]
drm/amd: Fix UBSAN array-index-out-of-bounds for Polaris and Tonga

For pptable structs that use flexible array sizes, use flexible arrays.

Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2036742
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/radeon: Fix UBSAN array-index-out-of-bounds for Radeon HD 5430
Mario Limonciello [Wed, 4 Oct 2023 20:22:53 +0000 (15:22 -0500)]
drm/radeon: Fix UBSAN array-index-out-of-bounds for Radeon HD 5430

For pptable structs that use flexible array sizes, use flexible arrays.

Suggested-by: Felix Held <felix.held@amd.com>
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2894
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amd: Fix UBSAN array-index-out-of-bounds for SMU7
Mario Limonciello [Wed, 4 Oct 2023 20:22:52 +0000 (15:22 -0500)]
drm/amd: Fix UBSAN array-index-out-of-bounds for SMU7

For pptable structs that use flexible array sizes, use flexible arrays.

Suggested-by: Felix Held <felix.held@amd.com>
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2874
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Annotate struct amdgpu_bo_list with __counted_by
Kees Cook [Tue, 3 Oct 2023 23:29:52 +0000 (16:29 -0700)]
drm/amdgpu: Annotate struct amdgpu_bo_list with __counted_by

Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for
array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
functions).

As found with Coccinelle[1], add __counted_by for struct amdgpu_bo_list.
Additionally, since the element count member must be set before accessing
the annotated flexible array member, move its initialization earlier.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Christian König" <christian.koenig@amd.com>
Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com>
Cc: David Airlie <airlied@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: "Gustavo A. R. Silva" <gustavoars@kernel.org>
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Cc: Felix Kuehling <Felix.Kuehling@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-hardening@vger.kernel.org
Link: https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Drop unnecessary return statements
Srinivasan Shanmugam [Sat, 30 Sep 2023 02:41:31 +0000 (08:11 +0530)]
drm/amdgpu: Drop unnecessary return statements

There is no reason to call return at the end of function that
returns void.

Fixes the below:

WARNING: void function return statements are not generally useful

Thus remove such a statement in the affected functions.

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agoDocumentation/amdgpu: Add board info details
Lijo Lazar [Thu, 28 Sep 2023 03:34:11 +0000 (09:04 +0530)]
Documentation/amdgpu: Add board info details

Add documentation for board info sysfs attribute.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Add sysfs attribute to get board info
Lijo Lazar [Thu, 28 Sep 2023 03:26:20 +0000 (08:56 +0530)]
drm/amdgpu: Add sysfs attribute to get board info

Add a sysfs attribute which shows the board form factor like OAM or
CEM.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Get package types for smuio v13.0
Lijo Lazar [Thu, 28 Sep 2023 03:21:06 +0000 (08:51 +0530)]
drm/amdgpu: Get package types for smuio v13.0

Add support to query package types supported in smuio v13.0 ASICs.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: Add more smuio v13.0.3 package types
Lijo Lazar [Thu, 28 Sep 2023 03:15:26 +0000 (08:45 +0530)]
drm/amdgpu: Add more smuio v13.0.3 package types

Expand support to get other board types like OAM or CEM.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
8 months agodrm/amdgpu: fix ip count query for xcp partitions
Sathishkumar S [Wed, 20 Sep 2023 14:49:44 +0000 (20:19 +0530)]
drm/amdgpu: fix ip count query for xcp partitions

fix wrong ip count INFO on spatial partitions. update the query
to return the instance count corresponding to the partition id.

v2:
 initialize variables only when required to be (Christian)
 move variable declarations to the beginning of function (Christian)

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>