wl18xx: print chip info during boot
authorVictor Goldenshtein <victorg@ti.com>
Tue, 12 Mar 2013 15:19:42 +0000 (17:19 +0200)
committerLuciano Coelho <coelho@ti.com>
Mon, 25 Mar 2013 10:33:12 +0000 (12:33 +0200)
Print board type, PG with metal and ROM versions.
This might help debugging HW related issues.

Signed-off-by: Victor Goldenshtein <victorg@ti.com>
Signed-off-by: Luciano Coelho <coelho@ti.com>
drivers/net/wireless/ti/wl18xx/main.c
drivers/net/wireless/ti/wl18xx/reg.h

index b670776f9bb271e21788ace8e3c5d1a59dcd6d8a..9fa692d110250bde779c627e66af87e10ba4f5f2 100644 (file)
@@ -1145,6 +1145,7 @@ static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
 {
        u32 fuse;
+       s8 rom = 0, metal = 0, pg_ver = 0, rdl_ver = 0;
        int ret;
 
        ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
@@ -1155,8 +1156,29 @@ static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
        if (ret < 0)
                goto out;
 
+       pg_ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
+       rom = (fuse & WL18XX_ROM_VER_MASK) >> WL18XX_ROM_VER_OFFSET;
+
+       if (rom <= 0xE)
+               metal = (fuse & WL18XX_METAL_VER_MASK) >>
+                       WL18XX_METAL_VER_OFFSET;
+       else
+               metal = (fuse & WL18XX_NEW_METAL_VER_MASK) >>
+                       WL18XX_NEW_METAL_VER_OFFSET;
+
+       ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse);
+       if (ret < 0)
+               goto out;
+
+       rdl_ver = (fuse & WL18XX_RDL_VER_MASK) >> WL18XX_RDL_VER_OFFSET;
+       if (rdl_ver > RDL_MAX)
+               rdl_ver = RDL_NONE;
+
+       wl1271_info("wl18xx HW: RDL %d, %s, PG %x.%x (ROM %x)",
+                   rdl_ver, rdl_names[rdl_ver], pg_ver, metal, rom);
+
        if (ver)
-               *ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
+               *ver = pg_ver;
 
        ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 
index 937b71d8783ff84a19ae52a04df4d25c1d98b6f9..6306e04cd2580676e6683ae62a64cecc3578c719 100644 (file)
 #define WL18XX_REG_FUSE_DATA_1_3       0xA0260C
 #define WL18XX_PG_VER_MASK             0x70
 #define WL18XX_PG_VER_OFFSET           4
+#define WL18XX_ROM_VER_MASK            0x3
+#define WL18XX_ROM_VER_OFFSET          0
+#define WL18XX_METAL_VER_MASK          0xC
+#define WL18XX_METAL_VER_OFFSET                2
+#define WL18XX_NEW_METAL_VER_MASK      0x180
+#define WL18XX_NEW_METAL_VER_OFFSET    7
+
+#define WL18XX_REG_FUSE_DATA_2_3       0xA02614
+#define WL18XX_RDL_VER_MASK            0x1f00
+#define WL18XX_RDL_VER_OFFSET          8
 
 #define WL18XX_REG_FUSE_BD_ADDR_1      0xA02602
 #define WL18XX_REG_FUSE_BD_ADDR_2      0xA02606
@@ -188,4 +198,23 @@ enum {
        NUM_BOARD_TYPES,
 };
 
+enum {
+       RDL_NONE        = 0,
+       RDL_1_HP        = 1,
+       RDL_2_SP        = 2,
+       RDL_3_HP        = 3,
+       RDL_4_SP        = 4,
+
+       _RDL_LAST,
+       RDL_MAX = _RDL_LAST - 1,
+};
+
+static const char * const rdl_names[] = {
+       [RDL_NONE]      = "",
+       [RDL_1_HP]      = "1853 SISO",
+       [RDL_2_SP]      = "1857 MIMO",
+       [RDL_3_HP]      = "1893 SISO",
+       [RDL_4_SP]      = "1897 MIMO",
+};
+
 #endif /* __REG_H__ */