ath10k: check all CE for data if irq summary is not retained
authorRakesh Pillai <pillair@codeaurora.org>
Tue, 10 Apr 2018 15:01:32 +0000 (18:01 +0300)
committerKalle Valo <kvalo@codeaurora.org>
Thu, 19 Apr 2018 15:52:57 +0000 (18:52 +0300)
WCN3990 has interrupts per CE and the interrupt summary
is not retained after the interrupt handler has finished
execution. We need to check if we received any
ce in rx and tx completion path.

Generate a interrupt summary with all CE interrupts if
the target does not retain interrupt summary after the
execution of interrupt handler.

Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
drivers/net/wireless/ath/ath10k/ce.h
drivers/net/wireless/ath/ath10k/core.c
drivers/net/wireless/ath/ath10k/hw.h

index 2c3c8f5e90ea0e499b2bf4f3b67c60a1e68186cb..d8f9da334529c189d2db91e99687a0c29d5bd880 100644 (file)
@@ -355,14 +355,18 @@ static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
        (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
                CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS                   0x0000
+#define CE_INTERRUPT_SUMMARY           (GENMASK(CE_COUNT_MAX - 1, 0))
 
 static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar)
 {
        struct ath10k_ce *ce = ath10k_ce_priv(ar);
 
-       return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
-               ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
-               CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
+       if (!ar->hw_params.per_ce_irq)
+               return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
+                       ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
+                       CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
+       else
+               return CE_INTERRUPT_SUMMARY;
 }
 
 #endif /* _CE_H_ */
index 6a9ad4ab8e4ce4c67230561ba56926ea559c6820..a21530dacc35b80c7d83e4d2f90b5157d999fee6 100644 (file)
@@ -119,6 +119,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .num_wds_entries = 0x20,
                .target_64bit = false,
                .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
+               .per_ce_irq = false,
        },
        {
                .id = QCA9887_HW_1_0_VERSION,
@@ -148,6 +149,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .num_wds_entries = 0x20,
                .target_64bit = false,
                .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
+               .per_ce_irq = false,
        },
        {
                .id = QCA6174_HW_2_1_VERSION,
@@ -176,6 +178,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .num_wds_entries = 0x20,
                .target_64bit = false,
                .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
+               .per_ce_irq = false,
        },
        {
                .id = QCA6174_HW_2_1_VERSION,
@@ -204,6 +207,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .num_wds_entries = 0x20,
                .target_64bit = false,
                .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
+               .per_ce_irq = false,
        },
        {
                .id = QCA6174_HW_3_0_VERSION,
@@ -232,6 +236,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .num_wds_entries = 0x20,
                .target_64bit = false,
                .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
+               .per_ce_irq = false,
        },
        {
                .id = QCA6174_HW_3_2_VERSION,
@@ -263,6 +268,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .num_wds_entries = 0x20,
                .target_64bit = false,
                .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
+               .per_ce_irq = false,
        },
        {
                .id = QCA99X0_HW_2_0_DEV_VERSION,
@@ -297,6 +303,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .num_wds_entries = 0x20,
                .target_64bit = false,
                .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
+               .per_ce_irq = false,
        },
        {
                .id = QCA9984_HW_1_0_DEV_VERSION,
@@ -336,6 +343,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .num_wds_entries = 0x20,
                .target_64bit = false,
                .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
+               .per_ce_irq = false,
        },
        {
                .id = QCA9888_HW_2_0_DEV_VERSION,
@@ -374,6 +382,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .num_wds_entries = 0x20,
                .target_64bit = false,
                .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
+               .per_ce_irq = false,
        },
        {
                .id = QCA9377_HW_1_0_DEV_VERSION,
@@ -402,6 +411,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .num_wds_entries = 0x20,
                .target_64bit = false,
                .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
+               .per_ce_irq = false,
        },
        {
                .id = QCA9377_HW_1_1_DEV_VERSION,
@@ -432,6 +442,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .num_wds_entries = 0x20,
                .target_64bit = false,
                .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
+               .per_ce_irq = false,
        },
        {
                .id = QCA4019_HW_1_0_DEV_VERSION,
@@ -467,6 +478,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .num_wds_entries = 0x20,
                .target_64bit = false,
                .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
+               .per_ce_irq = false,
        },
        {
                .id = WCN3990_HW_1_0_DEV_VERSION,
@@ -487,6 +499,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .num_wds_entries = TARGET_HL_10_TLV_NUM_WDS_ENTRIES,
                .target_64bit = true,
                .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
+               .per_ce_irq = true,
        },
 };
 
index 413b1b4321f77f7dfbd947844e1fad40d36f0e08..3041eba61e549f0f871b3e452919997ce3d07c8a 100644 (file)
@@ -568,6 +568,9 @@ struct ath10k_hw_params {
 
        /* Target rx ring fill level */
        u32 rx_ring_fill_level;
+
+       /* target supporting per ce IRQ */
+       bool per_ce_irq;
 };
 
 struct htt_rx_desc;