m68knommu: make ColdFire SYPCR and RSR register definitions absolute addresses

Make all definitions of the ColdFire Reset and System registers absolute
addresses. Currently some are relative to the MBAR peripheral region.

The various ColdFire parts use different methods to address the internal
registers, some are absolute, some are relative to peripheral regions
which can be mapped at different address ranges (such as the MBAR and IPSBAR
registers). We don't want to deal with this in the code when we are
accessing these registers, so make all register definitions the abolsute
address - factoring out whether it is an offset into a peripheral region.

This makes them all consistently defined, and reduces the occasional bugs
caused by inconsistent definition of the register addresses.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index e8bae33aed6052d6c2a6a5704cd927b99d0afd70..d67ce08e508d57e0d95848ff4e4ffa587c5a1bef 100644 (file)
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -43,8 +43,8 @@
 #define        MCFSIM_IMR              (MCF_MBAR + 0x36)       /* Interrupt Mask */
 #define        MCFSIM_IPR              (MCF_MBAR + 0x3a)       /* Interrupt Pending */
 
-#define        MCFSIM_RSR              0x40            /* Reset Status reg (r/w) */
-#define        MCFSIM_SYPCR            0x41            /* System Protection reg (r/w)*/
+#define        MCFSIM_RSR              (MCF_MBAR + 0x40)       /* Reset Status */
+#define        MCFSIM_SYPCR            (MCF_MBAR + 0x41)       /* System Protection */
 
 #define        MCFSIM_SWIVR            0x42            /* SW Watchdog intr reg (r/w) */
 #define        MCFSIM_SWSR             0x43            /* SW Watchdog service (r/w) */

diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index d0aa7f27a311dc7551a0f4e47240faae7b882c29..e57785de8a2a230ca1bd67fb8846c0996cfed279 100644 (file)
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -25,8 +25,8 @@
 /*
  *     Define the 5249 SIM register set addresses.
  */
-#define        MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define        MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
+#define        MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status */
+#define        MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
 #define        MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
 #define        MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
 #define        MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */

diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
index 0d6d192355ca02b36db648d49be28052d68aa369..05876cc95dde3f271c45effb89b6409d83ecd17e 100644 (file)
--- a/arch/m68k/include/asm/m525xsim.h
+++ b/arch/m68k/include/asm/m525xsim.h
@@ -26,8 +26,8 @@
 /*
  *     Define the 525x SIM register set addresses.
  */
-#define MCFSIM_RSR             0x00            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR           0x01            /* System Protection reg (r/w)*/
+#define MCFSIM_RSR             (MCF_MBAR + 0x00)       /* Reset Status */
+#define MCFSIM_SYPCR           (MCF_MBAR + 0x01)       /* System Protection */
 #define MCFSIM_SWIVR           0x02            /* SW Watchdog intr reg (r/w) */
 #define MCFSIM_SWSR            0x03            /* SW Watchdog service (r/w) */
 #define MCFSIM_MPARK           0x0C            /* BUS Master Control Reg*/

diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 255f7f3120d96271fc9275510eba84da6dd2efee..5709de5b8289d4eae45d49cb0743b4a3edb0a470 100644 (file)
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -23,8 +23,8 @@
 /*
  *     Define the 5307 SIM register set addresses.
  */
-#define        MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define        MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
+#define        MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status reg */
+#define        MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
 #define        MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
 #define        MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
 #define        MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */

diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index afdd56325ae7ccce6b1eb8c10b19718093d603f8..622ebface9b33667dbaef73a999df821995fd17b 100644 (file)
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -23,8 +23,8 @@
 /*
  *     Define the 5407 SIM register set addresses.
  */
-#define        MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
-#define        MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
+#define        MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status */
+#define        MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
 #define        MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
 #define        MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
 #define        MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */

diff --git a/arch/m68k/platform/coldfire/reset.c b/arch/m68k/platform/coldfire/reset.c
index 933e54eacc691dfc118d7281683c1c2907ed6887..f30952f0cbe6fee1757de6bd0cb3c186c49a236e 100644 (file)
--- a/arch/m68k/platform/coldfire/reset.c
+++ b/arch/m68k/platform/coldfire/reset.c
@@ -27,7 +27,7 @@ static void mcf_cpu_reset(void)
 {
        local_irq_disable();
        /* Set watchdog to soft reset, and enabled */
-       __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
+       __raw_writeb(0xc0, MCFSIM_SYPCR);
        for (;;)
                /* wait for watchdog to timeout */;
 }