drm/amd/display: add max scl ratio to soc bounding box

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 6943801c5fd3f5c509e7f181d87df2cb8914b6a2..c43d68bc9d5cd0df80772f111fcbfdac5d72bc87 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -111,6 +111,8 @@ struct _vcs_dpi_soc_bounding_box_st {
        double xfc_bus_transport_time_us;
        double xfc_xbuf_latency_tolerance_us;
        int use_urgent_burst_bw;
+       double max_hscl_ratio;
+       double max_vscl_ratio;
        struct _vcs_dpi_voltage_scaling_st clock_limits[7];
 };