clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel

The MUX clock of dpi1_sel should select the closet clock for itself.
We could add this flag to enable this function of MUX in CCF.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
Signed-off-by: wangyan wang <wangyan.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index ab6ab07f53e64b79cc7133929ebd3efb9bb1f71f..905a2316f6a7fd64bb4399ad936cf6277988aad6 100644 (file)
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -535,8 +535,8 @@ static const struct mtk_composite top_muxes[] = {
                0x0080, 8, 2, 15),
        MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
                0x0080, 16, 3, 23),
-       MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
-               0x0080, 24, 2, 31),
+       MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
+               0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST),
 
        MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
                0x0090, 0, 3, 7),