ARM: mvebu: Fix AXP-WiFi-AP DT for MBUS DT binding

The ranges property needs to be changed to use the new MBus DT binding.
Also, the pcie-controller node needs to be relocated as according the MBus
DT binding, it's now a child of the mbus-compatible node.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index 2a542bd20565a89bb5272f6fd890e4a570f87326..c5fe57269f5aca5c28f61de250dd5663298ec27e 100644 (file)
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -16,7 +16,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp-mv78230.dtsi"
+#include "armada-xp-mv78230.dtsi"
 
 / {
        model = "Marvell RD-AXPWiFiAP";
@@ -32,8 +32,30 @@
        };
 
        soc {
-               ranges = <0          0 0xf1000000 0x100000  /* Internal registers 1MiB */
-                         0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+                         MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+
+               pcie-controller {
+                       status = "okay";
+
+                       /* First mini-PCIe port */
+                       pcie@1,0 {
+                               /* Port 0, Lane 0 */
+                               status = "okay";
+                       };
+
+                       /* Second mini-PCIe port */
+                       pcie@2,0 {
+                               /* Port 0, Lane 1 */
+                               status = "okay";
+                       };
+
+                       /* Renesas uPD720202 USB 3.0 controller */
+                       pcie@3,0 {
+                               /* Port 0, Lane 3 */
+                               status = "okay";
+                       };
+               };
 
                internal-regs {
                        pinctrl {
@@ -123,28 +145,6 @@
                                        spi-max-frequency = <108000000>;
                                };
                        };
-
-                       pcie-controller {
-                               status = "okay";
-
-                               /* First mini-PCIe port */
-                               pcie@1,0 {
-                                       /* Port 0, Lane 0 */
-                                       status = "okay";
-                               };
-
-                               /* Second mini-PCIe port */
-                               pcie@2,0 {
-                                       /* Port 0, Lane 1 */
-                                       status = "okay";
-                               };
-
-                               /* Renesas uPD720202 USB 3.0 controller */
-                               pcie@3,0 {
-                                       /* Port 0, Lane 3 */
-                                       status = "okay";
-                               };
-                       };
                };
        };