Merge branch 'asoc-5.15' into asoc-5.16
authorMark Brown <broonie@kernel.org>
Mon, 18 Oct 2021 20:15:13 +0000 (21:15 +0100)
committerMark Brown <broonie@kernel.org>
Mon, 18 Oct 2021 20:15:13 +0000 (21:15 +0100)
12 files changed:
sound/soc/codecs/Kconfig
sound/soc/codecs/cs42l42.c
sound/soc/codecs/cs42l42.h
sound/soc/codecs/cs4341.c
sound/soc/codecs/nau8824.c
sound/soc/codecs/pcm179x-spi.c
sound/soc/codecs/pcm512x.c
sound/soc/codecs/wcd938x.c
sound/soc/codecs/wm8960.c
sound/soc/fsl/fsl_xcvr.c
sound/soc/soc-core.c
sound/soc/soc-dapm.c

index b58fd2aebe918d04251f154ccb6c890ef250f767..ab26b48341957207515374e5747c1a07d67a6e71 100644 (file)
@@ -1612,6 +1612,7 @@ config SND_SOC_WCD938X_SDW
        tristate "WCD9380/WCD9385 Codec - SDW"
        select SND_SOC_WCD938X
        select SND_SOC_WCD_MBHC
+       select REGMAP_IRQ
        depends on SOUNDWIRE
        select REGMAP_SOUNDWIRE
        help
index d484ec09eb2ebbbf9407b0347d2c333d610fbb95..5e4d6791756bcc01b4c002b054e890188805f2d1 100644 (file)
@@ -41,7 +41,6 @@
 static const struct reg_default cs42l42_reg_defaults[] = {
        { CS42L42_FRZ_CTL,                      0x00 },
        { CS42L42_SRC_CTL,                      0x10 },
-       { CS42L42_MCLK_STATUS,                  0x02 },
        { CS42L42_MCLK_CTL,                     0x02 },
        { CS42L42_SFTRAMP_RATE,                 0xA4 },
        { CS42L42_I2C_DEBOUNCE,                 0x88 },
@@ -53,15 +52,12 @@ static const struct reg_default cs42l42_reg_defaults[] = {
        { CS42L42_RSENSE_CTL1,                  0x40 },
        { CS42L42_RSENSE_CTL2,                  0x00 },
        { CS42L42_OSC_SWITCH,                   0x00 },
-       { CS42L42_OSC_SWITCH_STATUS,            0x05 },
        { CS42L42_RSENSE_CTL3,                  0x1B },
        { CS42L42_TSENSE_CTL,                   0x1B },
        { CS42L42_TSRS_INT_DISABLE,             0x00 },
-       { CS42L42_TRSENSE_STATUS,               0x00 },
        { CS42L42_HSDET_CTL1,                   0x77 },
        { CS42L42_HSDET_CTL2,                   0x00 },
        { CS42L42_HS_SWITCH_CTL,                0xF3 },
-       { CS42L42_HS_DET_STATUS,                0x00 },
        { CS42L42_HS_CLAMP_DISABLE,             0x00 },
        { CS42L42_MCLK_SRC_SEL,                 0x00 },
        { CS42L42_SPDIF_CLK_CFG,                0x00 },
@@ -75,25 +71,13 @@ static const struct reg_default cs42l42_reg_defaults[] = {
        { CS42L42_IN_ASRC_CLK,                  0x00 },
        { CS42L42_OUT_ASRC_CLK,                 0x00 },
        { CS42L42_PLL_DIV_CFG1,                 0x00 },
-       { CS42L42_ADC_OVFL_STATUS,              0x00 },
-       { CS42L42_MIXER_STATUS,                 0x00 },
-       { CS42L42_SRC_STATUS,                   0x00 },
-       { CS42L42_ASP_RX_STATUS,                0x00 },
-       { CS42L42_ASP_TX_STATUS,                0x00 },
-       { CS42L42_CODEC_STATUS,                 0x00 },
-       { CS42L42_DET_INT_STATUS1,              0x00 },
-       { CS42L42_DET_INT_STATUS2,              0x00 },
-       { CS42L42_SRCPL_INT_STATUS,             0x00 },
-       { CS42L42_VPMON_STATUS,                 0x00 },
-       { CS42L42_PLL_LOCK_STATUS,              0x00 },
-       { CS42L42_TSRS_PLUG_STATUS,             0x00 },
        { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
        { CS42L42_MIXER_INT_MASK,               0x0F },
        { CS42L42_SRC_INT_MASK,                 0x0F },
        { CS42L42_ASP_RX_INT_MASK,              0x1F },
        { CS42L42_ASP_TX_INT_MASK,              0x0F },
        { CS42L42_CODEC_INT_MASK,               0x03 },
-       { CS42L42_SRCPL_INT_MASK,               0xFF },
+       { CS42L42_SRCPL_INT_MASK,               0x7F },
        { CS42L42_VPMON_INT_MASK,               0x01 },
        { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
        { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
@@ -105,8 +89,6 @@ static const struct reg_default cs42l42_reg_defaults[] = {
        { CS42L42_PLL_CTL3,                     0x10 },
        { CS42L42_PLL_CAL_RATIO,                0x80 },
        { CS42L42_PLL_CTL4,                     0x03 },
-       { CS42L42_LOAD_DET_RCSTAT,              0x00 },
-       { CS42L42_LOAD_DET_DONE,                0x00 },
        { CS42L42_LOAD_DET_EN,                  0x00 },
        { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
        { CS42L42_WAKE_CTL,                     0xC0 },
@@ -115,8 +97,6 @@ static const struct reg_default cs42l42_reg_defaults[] = {
        { CS42L42_MISC_DET_CTL,                 0x03 },
        { CS42L42_MIC_DET_CTL1,                 0x1F },
        { CS42L42_MIC_DET_CTL2,                 0x2F },
-       { CS42L42_DET_STATUS1,                  0x00 },
-       { CS42L42_DET_STATUS2,                  0x00 },
        { CS42L42_DET_INT1_MASK,                0xE0 },
        { CS42L42_DET_INT2_MASK,                0xFF },
        { CS42L42_HS_BIAS_CTL,                  0xC2 },
@@ -130,7 +110,7 @@ static const struct reg_default cs42l42_reg_defaults[] = {
        { CS42L42_MIXER_CHA_VOL,                0x3F },
        { CS42L42_MIXER_ADC_VOL,                0x3F },
        { CS42L42_MIXER_CHB_VOL,                0x3F },
-       { CS42L42_EQ_COEF_IN0,                  0x22 },
+       { CS42L42_EQ_COEF_IN0,                  0x00 },
        { CS42L42_EQ_COEF_IN1,                  0x00 },
        { CS42L42_EQ_COEF_IN2,                  0x00 },
        { CS42L42_EQ_COEF_IN3,                  0x00 },
@@ -182,7 +162,6 @@ static const struct reg_default cs42l42_reg_defaults[] = {
        { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
        { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
        { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
-       { CS42L42_SUB_REVID,                    0x03 },
 };
 
 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
@@ -351,6 +330,7 @@ static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
        case CS42L42_DEVID_CD:
        case CS42L42_DEVID_E:
        case CS42L42_MCLK_STATUS:
+       case CS42L42_OSC_SWITCH_STATUS:
        case CS42L42_TRSENSE_STATUS:
        case CS42L42_HS_DET_STATUS:
        case CS42L42_ADC_OVFL_STATUS:
@@ -455,10 +435,36 @@ static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
                                0x3f, 1, mixer_tlv)
 };
 
+static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w,
+                            struct snd_kcontrol *kcontrol, int event)
+{
+       struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+       struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
+
+       switch (event) {
+       case SND_SOC_DAPM_PRE_PMU:
+               cs42l42->hp_adc_up_pending = true;
+               break;
+       case SND_SOC_DAPM_POST_PMU:
+               /* Only need one delay if HP and ADC are both powering-up */
+               if (cs42l42->hp_adc_up_pending) {
+                       usleep_range(CS42L42_HP_ADC_EN_TIME_US,
+                                    CS42L42_HP_ADC_EN_TIME_US + 1000);
+                       cs42l42->hp_adc_up_pending = false;
+               }
+               break;
+       default:
+               break;
+       }
+
+       return 0;
+}
+
 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
        /* Playback Path */
        SND_SOC_DAPM_OUTPUT("HP"),
-       SND_SOC_DAPM_DAC("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1),
+       SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1,
+                          cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
        SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
        SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0),
        SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0),
@@ -468,7 +474,8 @@ static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
 
        /* Capture Path */
        SND_SOC_DAPM_INPUT("HS"),
-       SND_SOC_DAPM_ADC("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1),
+       SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1,
+                          cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
        SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
        SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
 
@@ -517,12 +524,6 @@ static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_
 
        cs42l42->jack = jk;
 
-       regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
-                          CS42L42_RS_PLUG_MASK | CS42L42_RS_UNPLUG_MASK |
-                          CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK,
-                          (1 << CS42L42_RS_PLUG_SHIFT) | (1 << CS42L42_RS_UNPLUG_SHIFT) |
-                          (0 << CS42L42_TS_PLUG_SHIFT) | (0 << CS42L42_TS_UNPLUG_SHIFT));
-
        return 0;
 }
 
@@ -569,7 +570,6 @@ static const struct reg_sequence cs42l42_to_osc_seq[] = {
 
 struct cs42l42_pll_params {
        u32 sclk;
-       u8 mclk_div;
        u8 mclk_src_sel;
        u8 sclk_prediv;
        u8 pll_div_int;
@@ -586,24 +586,24 @@ struct cs42l42_pll_params {
  * Table 4-5 from the Datasheet
  */
 static const struct cs42l42_pll_params pll_ratio_table[] = {
-       { 1411200, 0, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
-       { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
-       { 2304000, 0, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000,  85, 2},
-       { 2400000, 0, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
-       { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
-       { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
-       { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
-       { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000,  96, 1},
-       { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000,  94, 1},
-       { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
-       { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
-       { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
-       { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
-       { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
-       { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
-       { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0, 1},
-       { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0, 1},
-       { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0, 1}
+       { 1411200,  1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
+       { 1536000,  1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
+       { 2304000,  1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000,  85, 2},
+       { 2400000,  1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
+       { 2822400,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
+       { 3000000,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
+       { 3072000,  1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
+       { 4000000,  1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000,  96, 1},
+       { 4096000,  1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000,  94, 1},
+       { 5644800,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
+       { 6000000,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
+       { 6144000,  1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
+       { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
+       { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
+       { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
+       { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
+       { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
+       { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}
 };
 
 static int cs42l42_pll_config(struct snd_soc_component *component)
@@ -618,6 +618,14 @@ static int cs42l42_pll_config(struct snd_soc_component *component)
        else
                clk = cs42l42->sclk;
 
+       /* Don't reconfigure if there is an audio stream running */
+       if (cs42l42->stream_use) {
+               if (pll_ratio_table[cs42l42->pll_config].sclk == clk)
+                       return 0;
+               else
+                       return -EBUSY;
+       }
+
        for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
                if (pll_ratio_table[i].sclk == clk) {
                        cs42l42->pll_config = i;
@@ -631,10 +639,6 @@ static int cs42l42_pll_config(struct snd_soc_component *component)
                                        24000000)) <<
                                        CS42L42_INTERNAL_FS_SHIFT);
 
-                       snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL,
-                                       CS42L42_MCLKDIV_MASK,
-                                       (pll_ratio_table[i].mclk_div <<
-                                       CS42L42_MCLKDIV_SHIFT));
                        /* Set up the LRCLK */
                        fsync = clk / cs42l42->srate;
                        if (((fsync * cs42l42->srate) != clk)
@@ -668,22 +672,6 @@ static int cs42l42_pll_config(struct snd_soc_component *component)
                                        CS42L42_FSYNC_PULSE_WIDTH_MASK,
                                        CS42L42_FRAC1_VAL(fsync - 1) <<
                                        CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
-                       /* Set the sample rates (96k or lower) */
-                       snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
-                                       CS42L42_FS_EN_MASK,
-                                       (CS42L42_FS_EN_IASRC_96K |
-                                       CS42L42_FS_EN_OASRC_96K) <<
-                                       CS42L42_FS_EN_SHIFT);
-                       /* Set the input/output internal MCLK clock ~12 MHz */
-                       snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
-                                       CS42L42_CLK_IASRC_SEL_MASK,
-                                       CS42L42_CLK_IASRC_SEL_12 <<
-                                       CS42L42_CLK_IASRC_SEL_SHIFT);
-                       snd_soc_component_update_bits(component,
-                                       CS42L42_OUT_ASRC_CLK,
-                                       CS42L42_CLK_OASRC_SEL_MASK,
-                                       CS42L42_CLK_OASRC_SEL_12 <<
-                                       CS42L42_CLK_OASRC_SEL_SHIFT);
                        if (pll_ratio_table[i].mclk_src_sel == 0) {
                                /* Pass the clock straight through */
                                snd_soc_component_update_bits(component,
@@ -746,6 +734,39 @@ static int cs42l42_pll_config(struct snd_soc_component *component)
        return -EINVAL;
 }
 
+static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
+{
+       struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
+       unsigned int fs;
+
+       /* Don't reconfigure if there is an audio stream running */
+       if (cs42l42->stream_use)
+               return;
+
+       /* SRC MCLK must be as close as possible to 125 * sample rate */
+       if (sample_rate <= 48000)
+               fs = CS42L42_CLK_IASRC_SEL_6;
+       else
+               fs = CS42L42_CLK_IASRC_SEL_12;
+
+       /* Set the sample rates (96k or lower) */
+       snd_soc_component_update_bits(component,
+                                     CS42L42_FS_RATE_EN,
+                                     CS42L42_FS_EN_MASK,
+                                     (CS42L42_FS_EN_IASRC_96K |
+                                      CS42L42_FS_EN_OASRC_96K) <<
+                                     CS42L42_FS_EN_SHIFT);
+
+       snd_soc_component_update_bits(component,
+                                     CS42L42_IN_ASRC_CLK,
+                                     CS42L42_CLK_IASRC_SEL_MASK,
+                                     fs << CS42L42_CLK_IASRC_SEL_SHIFT);
+       snd_soc_component_update_bits(component,
+                                     CS42L42_OUT_ASRC_CLK,
+                                     CS42L42_CLK_OASRC_SEL_MASK,
+                                     fs << CS42L42_CLK_OASRC_SEL_SHIFT);
+}
+
 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 {
        struct snd_soc_component *component = codec_dai->component;
@@ -824,7 +845,7 @@ static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_s
        /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */
        return snd_pcm_hw_constraint_minmax(substream->runtime,
                                            SNDRV_PCM_HW_PARAM_RATE,
-                                           44100, 192000);
+                                           44100, 96000);
 }
 
 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
@@ -836,6 +857,7 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
        unsigned int channels = params_channels(params);
        unsigned int width = (params_width(params) / 8) - 1;
        unsigned int val = 0;
+       int ret;
 
        cs42l42->srate = params_rate(params);
        cs42l42->bclk = snd_soc_params_to_bclk(params);
@@ -853,11 +875,10 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 
        switch (substream->stream) {
        case SNDRV_PCM_STREAM_CAPTURE:
-               if (channels == 2) {
-                       val |= CS42L42_ASP_TX_CH2_AP_MASK;
-                       val |= width << CS42L42_ASP_TX_CH2_RES_SHIFT;
-               }
-               val |= width << CS42L42_ASP_TX_CH1_RES_SHIFT;
+               /* channel 2 on high LRCLK */
+               val = CS42L42_ASP_TX_CH2_AP_MASK |
+                     (width << CS42L42_ASP_TX_CH2_RES_SHIFT) |
+                     (width << CS42L42_ASP_TX_CH1_RES_SHIFT);
 
                snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
                                CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
@@ -890,7 +911,13 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
                break;
        }
 
-       return cs42l42_pll_config(component);
+       ret = cs42l42_pll_config(component);
+       if (ret)
+               return ret;
+
+       cs42l42_src_config(component, params_rate(params));
+
+       return 0;
 }
 
 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
@@ -922,7 +949,6 @@ static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
        struct snd_soc_component *component = dai->component;
        struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
        unsigned int regval;
-       u8 fullScaleVol;
        int ret;
 
        if (mute) {
@@ -993,20 +1019,11 @@ static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
                cs42l42->stream_use |= 1 << stream;
 
                if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
-                       /* Read the headphone load */
-                       regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT);
-                       if (((regval & CS42L42_RLA_STAT_MASK) >> CS42L42_RLA_STAT_SHIFT) ==
-                           CS42L42_RLA_STAT_15_OHM) {
-                               fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK;
-                       } else {
-                               fullScaleVol = 0;
-                       }
-
-                       /* Un-mute the headphone, set the full scale volume flag */
+                       /* Un-mute the headphone */
                        snd_soc_component_update_bits(component, CS42L42_HP_CTL,
                                                      CS42L42_HP_ANA_AMUTE_MASK |
-                                                     CS42L42_HP_ANA_BMUTE_MASK |
-                                                     CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol);
+                                                     CS42L42_HP_ANA_BMUTE_MASK,
+                                                     0);
                }
        }
 
@@ -1031,14 +1048,14 @@ static struct snd_soc_dai_driver cs42l42_dai = {
                        .stream_name = "Playback",
                        .channels_min = 1,
                        .channels_max = 2,
-                       .rates = SNDRV_PCM_RATE_8000_192000,
+                       .rates = SNDRV_PCM_RATE_8000_96000,
                        .formats = CS42L42_FORMATS,
                },
                .capture = {
                        .stream_name = "Capture",
                        .channels_min = 1,
                        .channels_max = 2,
-                       .rates = SNDRV_PCM_RATE_8000_192000,
+                       .rates = SNDRV_PCM_RATE_8000_96000,
                        .formats = CS42L42_FORMATS,
                },
                .symmetric_rate = 1,
@@ -1786,8 +1803,8 @@ static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
                        CS42L42_TS_UNPLUG_MASK,
                        (1 << CS42L42_RS_PLUG_SHIFT) |
                        (1 << CS42L42_RS_UNPLUG_SHIFT) |
-                       (1 << CS42L42_TS_PLUG_SHIFT) |
-                       (1 << CS42L42_TS_UNPLUG_SHIFT));
+                       (0 << CS42L42_TS_PLUG_SHIFT) |
+                       (0 << CS42L42_TS_UNPLUG_SHIFT));
 }
 
 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
@@ -2070,16 +2087,21 @@ static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
        }
        usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
 
-       /* Request IRQ */
-       ret = devm_request_threaded_irq(&i2c_client->dev,
-                       i2c_client->irq,
-                       NULL, cs42l42_irq_thread,
-                       IRQF_ONESHOT | IRQF_TRIGGER_LOW,
-                       "cs42l42", cs42l42);
-
-       if (ret != 0)
-               dev_err(&i2c_client->dev,
-                       "Failed to request IRQ: %d\n", ret);
+       /* Request IRQ if one was specified */
+       if (i2c_client->irq) {
+               ret = devm_request_threaded_irq(&i2c_client->dev,
+                                               i2c_client->irq,
+                                               NULL, cs42l42_irq_thread,
+                                               IRQF_ONESHOT | IRQF_TRIGGER_LOW,
+                                               "cs42l42", cs42l42);
+               if (ret == -EPROBE_DEFER) {
+                       goto err_disable;
+               } else if (ret != 0) {
+                       dev_err(&i2c_client->dev,
+                               "Failed to request IRQ: %d\n", ret);
+                       goto err_disable;
+               }
+       }
 
        /* initialize codec */
        devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
@@ -2150,7 +2172,9 @@ static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
 {
        struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
 
-       devm_free_irq(&i2c_client->dev, i2c_client->irq, cs42l42);
+       if (i2c_client->irq)
+               devm_free_irq(&i2c_client->dev, i2c_client->irq, cs42l42);
+
        pm_runtime_suspend(&i2c_client->dev);
        pm_runtime_disable(&i2c_client->dev);
 
index 0704c902475fb0ef8e53b1c197dd6756c6b677e0..dd4744de9e0a6f7396e530acd69d2e3a0414a062 100644 (file)
 #define CS42L42_IN_ASRC_CLK            (CS42L42_PAGE_12 + 0x0A)
 #define CS42L42_CLK_IASRC_SEL_SHIFT    0
 #define CS42L42_CLK_IASRC_SEL_MASK     (1 << CS42L42_CLK_IASRC_SEL_SHIFT)
+#define CS42L42_CLK_IASRC_SEL_6                0
 #define CS42L42_CLK_IASRC_SEL_12       1
 
 #define CS42L42_OUT_ASRC_CLK           (CS42L42_PAGE_12 + 0x0B)
 #define CS42L42_CLOCK_SWITCH_DELAY_US 150
 #define CS42L42_PLL_LOCK_POLL_US       250
 #define CS42L42_PLL_LOCK_TIMEOUT_US    1250
+#define CS42L42_HP_ADC_EN_TIME_US      20000
 
 static const char *const cs42l42_supply_names[CS42L42_NUM_SUPPLIES] = {
        "VA",
@@ -853,6 +855,7 @@ struct  cs42l42_private {
        u8 hs_bias_ramp_time;
        u8 hs_bias_sense_en;
        u8 stream_use;
+       bool hp_adc_up_pending;
 };
 
 #endif /* __CS42L42_H__ */
index 7d3e54d8eef36f46f15b3b3d92c1469b70377416..29d05e32d3417f0879036bac718354a1e33010ff 100644 (file)
@@ -305,12 +305,19 @@ static int cs4341_spi_probe(struct spi_device *spi)
        return cs4341_probe(&spi->dev);
 }
 
+static const struct spi_device_id cs4341_spi_ids[] = {
+       { "cs4341a" },
+       { }
+};
+MODULE_DEVICE_TABLE(spi, cs4341_spi_ids);
+
 static struct spi_driver cs4341_spi_driver = {
        .driver = {
                .name = "cs4341-spi",
                .of_match_table = of_match_ptr(cs4341_dt_ids),
        },
        .probe = cs4341_spi_probe,
+       .id_table = cs4341_spi_ids,
 };
 #endif
 
index ffb3881aa40f65c199ebf5724135da7f0f7bca4d..d0dd1542f78a780864232bfc134d3ae7bb61181c 100644 (file)
@@ -875,8 +875,8 @@ static void nau8824_jdet_work(struct work_struct *work)
        struct regmap *regmap = nau8824->regmap;
        int adc_value, event = 0, event_mask = 0;
 
-       snd_soc_dapm_enable_pin(dapm, "MICBIAS");
-       snd_soc_dapm_enable_pin(dapm, "SAR");
+       snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
+       snd_soc_dapm_force_enable_pin(dapm, "SAR");
        snd_soc_dapm_sync(dapm);
 
        msleep(100);
index 0a542924ec5f969a94d236e2414e3684f7a744c7..ebf63ea90a1c4c7097f37383f0654b92e75fcc9e 100644 (file)
@@ -36,6 +36,7 @@ static const struct of_device_id pcm179x_of_match[] = {
 MODULE_DEVICE_TABLE(of, pcm179x_of_match);
 
 static const struct spi_device_id pcm179x_spi_ids[] = {
+       { "pcm1792a", 0 },
        { "pcm179x", 0 },
        { },
 };
index 4dc844f3c1fc0a95ac0f734939eb022488a0f847..60dee41816dc29369a371a8afc09a49821993244 100644 (file)
@@ -116,6 +116,8 @@ static const struct reg_default pcm512x_reg_defaults[] = {
        { PCM512x_FS_SPEED_MODE,     0x00 },
        { PCM512x_IDAC_1,            0x01 },
        { PCM512x_IDAC_2,            0x00 },
+       { PCM512x_I2S_1,             0x02 },
+       { PCM512x_I2S_2,             0x00 },
 };
 
 static bool pcm512x_readable(struct device *dev, unsigned int reg)
index f0daf8defcf1edd84b36ea037fe02a1ad7c19c98..52de7d14b13985970d44bb3f36203bfc9545d600 100644 (file)
@@ -4144,10 +4144,10 @@ static int wcd938x_codec_set_jack(struct snd_soc_component *comp,
 {
        struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev);
 
-       if (!jack)
+       if (jack)
                return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack);
-
-       wcd_mbhc_stop(wcd->wcd_mbhc);
+       else
+               wcd_mbhc_stop(wcd->wcd_mbhc);
 
        return 0;
 }
index 9e621a254392c77f6747b2a947b5f94505eb3b86..499604f1e178951026f30b3164f335b27a843323 100644 (file)
@@ -742,9 +742,16 @@ static int wm8960_configure_clocking(struct snd_soc_component *component)
        int i, j, k;
        int ret;
 
-       if (!(iface1 & (1<<6))) {
-               dev_dbg(component->dev,
-                       "Codec is slave mode, no need to configure clock\n");
+       /*
+        * For Slave mode clocking should still be configured,
+        * so this if statement should be removed, but some platform
+        * may not work if the sysclk is not configured, to avoid such
+        * compatible issue, just add '!wm8960->sysclk' condition in
+        * this if statement.
+        */
+       if (!(iface1 & (1 << 6)) && !wm8960->sysclk) {
+               dev_warn(component->dev,
+                        "slave mode, but proceeding with no clock configuration\n");
                return 0;
        }
 
index 7ba2fd15132d9b966e4b86d5459c707e880aac26..d0556c79fdb1531aaa6f84d53c2e6fcc3da82c24 100644 (file)
@@ -487,8 +487,9 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream,
                return ret;
        }
 
-       /* clear DPATH RESET */
+       /* set DPATH RESET */
        m_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
+       v_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
        ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl);
        if (ret < 0) {
                dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret);
@@ -590,10 +591,6 @@ static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream,
                val  |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
        }
 
-       /* set DPATH RESET */
-       mask |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
-       val  |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
-
        ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
        if (ret < 0) {
                dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret);
@@ -643,6 +640,16 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
                        dev_err(dai->dev, "Failed to enable DMA: %d\n", ret);
                        return ret;
                }
+
+               /* clear DPATH RESET */
+               ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
+                                        FSL_XCVR_EXT_CTRL_DPTH_RESET(tx),
+                                        0);
+               if (ret < 0) {
+                       dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret);
+                       return ret;
+               }
+
                break;
        case SNDRV_PCM_TRIGGER_STOP:
        case SNDRV_PCM_TRIGGER_SUSPEND:
index bdbaf14dc9fcc83bd76bac99063377e8139bd950..94f1548b8a3275ac8a89fe6de4537f92b1c399bb 100644 (file)
@@ -2578,6 +2578,7 @@ int snd_soc_component_initialize(struct snd_soc_component *component,
        INIT_LIST_HEAD(&component->dai_list);
        INIT_LIST_HEAD(&component->dobj_list);
        INIT_LIST_HEAD(&component->card_list);
+       INIT_LIST_HEAD(&component->list);
        mutex_init(&component->io_mutex);
 
        component->name = fmt_single_name(dev, &component->id);
index 44c4d105ffdb1a3b20481e56c0a8a095c6e60d70..2892b0aba151c083b71900eae31e70d5fd60ef0f 100644 (file)
@@ -2563,6 +2563,7 @@ static int snd_soc_dapm_set_pin(struct snd_soc_dapm_context *dapm,
                                const char *pin, int status)
 {
        struct snd_soc_dapm_widget *w = dapm_find_widget(dapm, pin, true);
+       int ret = 0;
 
        dapm_assert_locked(dapm);
 
@@ -2575,13 +2576,14 @@ static int snd_soc_dapm_set_pin(struct snd_soc_dapm_context *dapm,
                dapm_mark_dirty(w, "pin configuration");
                dapm_widget_invalidate_input_paths(w);
                dapm_widget_invalidate_output_paths(w);
+               ret = 1;
        }
 
        w->connected = status;
        if (status == 0)
                w->force = 0;
 
-       return 0;
+       return ret;
 }
 
 /**
@@ -3585,14 +3587,15 @@ int snd_soc_dapm_put_pin_switch(struct snd_kcontrol *kcontrol,
 {
        struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
        const char *pin = (const char *)kcontrol->private_value;
+       int ret;
 
        if (ucontrol->value.integer.value[0])
-               snd_soc_dapm_enable_pin(&card->dapm, pin);
+               ret = snd_soc_dapm_enable_pin(&card->dapm, pin);
        else
-               snd_soc_dapm_disable_pin(&card->dapm, pin);
+               ret = snd_soc_dapm_disable_pin(&card->dapm, pin);
 
        snd_soc_dapm_sync(&card->dapm);
-       return 0;
+       return ret;
 }
 EXPORT_SYMBOL_GPL(snd_soc_dapm_put_pin_switch);
 
@@ -4025,7 +4028,7 @@ static int snd_soc_dapm_dai_link_put(struct snd_kcontrol *kcontrol,
 
        rtd->params_select = ucontrol->value.enumerated.item[0];
 
-       return 0;
+       return 1;
 }
 
 static void