Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

The phylink conflict was between a bug fix by Russell King
to make sure we have a consistent PHY interface mode, and
a change in net-next to pull some code in phylink_resolve()
into the helper functions phylink_mac_link_{up,down}()

On the dp83867 side it's mostly overlapping changes, with
the 'net' side removing a condition that was supposed to
trigger for RGMII but because of how it was coded never
actually could trigger.

Signed-off-by: David S. Miller <davem@davemloft.net>

diff --cc Documentation/ABI/testing/sysfs-class-net-phydev
Simple merge

diff --cc drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
Simple merge

diff --cc drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
Simple merge

diff --cc drivers/net/ethernet/freescale/fec_main.c
Simple merge

diff --cc drivers/net/ethernet/marvell/mvneta.c
Simple merge

diff --cc drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c
Simple merge

diff --cc drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
Simple merge

diff --cc drivers/net/ethernet/mscc/ocelot.c
Simple merge

diff --cc drivers/net/ethernet/mscc/ocelot.h
Simple merge

diff --cc drivers/net/ethernet/realtek/r8169.c
Simple merge

diff --cc drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
Simple merge

diff --cc drivers/net/phy/dp83867.c
index 3bdf94043693f69838734aeb8db878eeb6be8ff3,c71c7d0f53f0a189fa503659aa10577d537ac975..1f1ecee0ee2f27c518fa3a22ce560d889aa0b53a
--- 1/drivers/net/phy/dp83867.c
--- 2/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@@ -26,11 -26,18 +26,19 @@@
  
  /* Extended Registers */
  #define DP83867_CFG4            0x0031
+ #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
+ #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS   (3 << 5)
+ #define DP83867_CFG4_SGMII_ANEG_TIMER_800US  (2 << 5)
+ #define DP83867_CFG4_SGMII_ANEG_TIMER_2US    (1 << 5)
+ #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS   (0 << 5)
+ 
  #define DP83867_RGMIICTL      0x0032
  #define DP83867_STRAP_STS1    0x006E
 +#define DP83867_STRAP_STS2    0x006f
  #define DP83867_RGMIIDCTL     0x0086
  #define DP83867_IO_MUX_CFG    0x0170
+ #define DP83867_10M_SGMII_CFG   0x016F
+ #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
  
  #define DP83867_SW_RESET      BIT(15)
  #define DP83867_SW_RESTART    BIT(14)
@@@ -321,18 -255,10 +329,17 @@@ static int dp83867_config_init(struct p
                ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
                if (ret)
                        return ret;
-       }
  
-       /* If rgmii mode with no internal delay is selected, we do NOT use
-        * aligned mode as one might expect.  Instead we use the PHY's default
-        * based on pin strapping.  And the "mode 0" default is to *use*
-        * internal delay with a value of 7 (2.00 ns).
-        */
-       if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
-           (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
 -              /* Set up RGMII delays */
++              /* If rgmii mode with no internal delay is selected, we do NOT use
++               * aligned mode as one might expect.  Instead we use the PHY's default
++               * based on pin strapping.  And the "mode 0" default is to *use*
++               * internal delay with a value of 7 (2.00 ns).
++               *
++               * Set up RGMII delays
++               */
                val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
  
 +              val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
                if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
                        val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
  
@@@ -349,14 -275,41 +356,41 @@@
  
                phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
                              delay);
 -
 -              if (dp83867->io_impedance >= 0)
 -                      phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 -                                     DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
 -                                     dp83867->io_impedance &
 -                                     DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
        }
  
 +      /* If specified, set io impedance */
 +      if (dp83867->io_impedance >= 0)
 +              phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 +                             DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
 +                             dp83867->io_impedance);
 +
+       if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+               /* For support SPEED_10 in SGMII mode
+                * DP83867_10M_SGMII_RATE_ADAPT bit
+                * has to be cleared by software. That
+                * does not affect SPEED_100 and
+                * SPEED_1000.
+                */
+               ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
+                                    DP83867_10M_SGMII_CFG,
+                                    DP83867_10M_SGMII_RATE_ADAPT_MASK,
+                                    0);
+               if (ret)
+                       return ret;
+ 
+               /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
+                * are 01). That is not enough to finalize autoneg on some
+                * devices. Increase this timer duration to maximum 16ms.
+                */
+               ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
+                                    DP83867_CFG4,
+                                    DP83867_CFG4_SGMII_ANEG_MASK,
+                                    DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
+ 
+               if (ret)
+                       return ret;
+       }
+ 
        /* Enable Interrupt output INT_OE in CFG3 register */
        if (phy_interrupt_is_valid(phydev)) {
                val = phy_read(phydev, DP83867_CFG3);

diff --cc drivers/net/phy/phylink.c
index 68d0a89c52be1abe6b8ada2790974bdd41444e00,9044b95d2afefaa2c8a21c796aa59262175209c7..b7300ea2663c47b4bac1e3f7875c564710206ab7
--- 1/drivers/net/phy/phylink.c
--- 2/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@@ -414,36 -399,6 +418,37 @@@ static const char *phylink_pause_to_str
        }
  }
  
-                              pl->phy_state.interface);
 +static void phylink_mac_link_up(struct phylink *pl,
 +                              struct phylink_link_state link_state)
 +{
 +      struct net_device *ndev = pl->netdev;
 +
++      pl->cur_interface = link_state.interface;
 +      pl->ops->mac_link_up(pl->config, pl->link_an_mode,
 +                           pl->phy_state.interface,
 +                           pl->phydev);
 +
 +      if (ndev)
 +              netif_carrier_on(ndev);
 +
 +      phylink_info(pl,
 +                   "Link is Up - %s/%s - flow control %s\n",
 +                   phy_speed_to_str(link_state.speed),
 +                   phy_duplex_to_str(link_state.duplex),
 +                   phylink_pause_to_str(link_state.pause));
 +}
 +
 +static void phylink_mac_link_down(struct phylink *pl)
 +{
 +      struct net_device *ndev = pl->netdev;
 +
 +      if (ndev)
 +              netif_carrier_off(ndev);
 +      pl->ops->mac_link_down(pl->config, pl->link_an_mode,
++                             pl->cur_interface);
 +      phylink_info(pl, "Link is Down\n");
 +}
 +
  static void phylink_resolve(struct work_struct *w)
  {
        struct phylink *pl = container_of(w, struct phylink, resolve);

diff --cc include/net/sctp/checksum.h
Simple merge

diff --cc net/core/skbuff.c
Simple merge

diff --cc net/ipv4/ip_output.c
Simple merge

diff --cc net/ipv6/addrconf.c
Simple merge

diff --cc net/ipv6/ip6_output.c
Simple merge

diff --cc net/ipv6/route.c
Simple merge

diff --cc tools/testing/selftests/net/pmtu.sh
index ab77e6344d174f7421425eead5e6703d6068bed9,317dafcd605d63b324a2ba59d5d9e0f1c49d4309..4a1275990d7e630b2797b04bdbdf23f51315d19e
--- 1/tools/testing/selftests/net/pmtu.sh
--- 2/tools/testing/selftests/net/pmtu.sh
+++ b/tools/testing/selftests/net/pmtu.sh
@@@ -208,10 -208,11 +208,10 @@@ tunnel6_a_addr="fd00:2::a
  tunnel6_b_addr="fd00:2::b"
  tunnel6_mask="64"
  
- dummy6_0_addr="fc00:1000::0"
- dummy6_1_addr="fc00:1001::0"
+ dummy6_0_prefix="fc00:1000::"
+ dummy6_1_prefix="fc00:1001::"
  dummy6_mask="64"
  
 -cleanup_done=1
  err_buf=
  tcpdump_pids=