* Licensed under the X11 license or the GPL v2 (or later)
*/
-#include "skeleton.dtsi"
#include <dt-bindings/clock/alphascale,asm9260.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
interrupt-parent = <&icoll>;
memory {
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton64.dtsi"
/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
/* SOC compatibility */
compatible = "al,alpine";
+ memory {
+ device_type = "memory";
+ reg = <0 0 0 0>;
+ };
+
/* CPU Configuration */
cpus {
#address-cells = <1>;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "arm,realview-eb";
chosen { };
};
memory {
+ device_type = "memory";
/* 128 MiB memory @ 0x0 */
reg = <0x00000000 0x08000000>;
};
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "ARM RealView PB1176";
compatible = "arm,realview-pb1176";
};
memory {
+ device_type = "memory";
/* 128 MiB memory @ 0x0 */
reg = <0x00000000 0x08000000>;
};
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "ARM RealView PB11MPcore";
compatible = "arm,realview-pb11mp";
};
memory {
+ device_type = "memory";
/*
* The PB11MPCore has 512 MiB memory @ 0x70000000
* and the first 256 are also remapped @ 0x00000000
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "arm,realview-pbx";
chosen { };
};
memory {
+ device_type = "memory";
/* 128 MiB memory @ 0x0 */
reg = <0x00000000 0x08000000>;
};
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*/
-#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
model = "Marvell Armada 38x family SoC";
compatible = "marvell,armada380";
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*/
-#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Marvell Armada 39x family SoC";
compatible = "marvell,armada390";
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/dma/nbpfaxi.h>
#include <dt-bindings/clock/axis,artpec6-clkctrl.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "axis,artpec6";
interrupt-parent = <&intc>;
* Licensed under GPLv2 or later.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Atmel AT91RM9200 family SoC";
compatible = "atmel,at91rm9200";
interrupt-parent = <&aic>;
};
memory {
+ device_type = "memory";
reg = <0x20000000 0x04000000>;
};
* Licensed under GPLv2 or later.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Atmel AT91SAM9260 family SoC";
compatible = "atmel,at91sam9260";
interrupt-parent = <&aic>;
};
memory {
+ device_type = "memory";
reg = <0x20000000 0x04000000>;
};
* Licensed under GPLv2 only.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Atmel AT91SAM9261 family SoC";
compatible = "atmel,at91sam9261";
interrupt-parent = <&aic>;
};
memory {
+ device_type = "memory";
reg = <0x20000000 0x08000000>;
};
* Licensed under GPLv2 only.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Atmel AT91SAM9263 family SoC";
compatible = "atmel,at91sam9263";
interrupt-parent = <&aic>;
};
memory {
+ device_type = "memory";
reg = <0x20000000 0x08000000>;
};
* Licensed under GPLv2 or later.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Atmel AT91SAM9G45 family SoC";
compatible = "atmel,at91sam9g45";
interrupt-parent = <&aic>;
};
memory {
+ device_type = "memory";
reg = <0x70000000 0x10000000>;
};
* Licensed under GPLv2 or later.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Atmel AT91SAM9N12 SoC";
compatible = "atmel,at91sam9n12";
interrupt-parent = <&aic>;
};
memory {
+ device_type = "memory";
reg = <0x20000000 0x10000000>;
};
* Licensed under GPLv2 or later.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Atmel AT91SAM9RL family SoC";
compatible = "atmel,at91sam9rl", "atmel,at91sam9";
interrupt-parent = <&aic>;
};
memory {
+ device_type = "memory";
reg = <0x20000000 0x04000000>;
};
* Licensed under GPLv2 or later.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Atmel AT91SAM9x5 family SoC";
compatible = "atmel,at91sam9x5";
interrupt-parent = <&aic>;
};
memory {
+ device_type = "memory";
reg = <0x20000000 0x10000000>;
};
compatible = "sirf,atlas6-cb", "sirf,atlas6";
memory {
+ device_type = "memory";
reg = <0x00000000 0x20000000>;
};
* Licensed under GPLv2 or later.
*/
-/include/ "skeleton.dtsi"
/ {
compatible = "sirf,atlas6";
#address-cells = <1>;
* Licensed under GPLv2 or later.
*/
-/include/ "skeleton.dtsi"
/ {
compatible = "sirf,atlas7";
#address-cells = <1>;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/lsi,axm5516-clks.h>
-#include "skeleton64.dtsi"
-
/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
interrupt-parent = <&gic>;
aliases {
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/bcm-cygnus.h>
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "brcm,cygnus";
model = "Broadcom Cygnus SoC";
interrupt-parent = <&gic>;
ethernet0 = ð0;
};
+ memory {
+ device_type = "memory";
+ reg = <0 0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/bcm-nsp.h>
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "brcm,nsp";
model = "Broadcom Northstar Plus SoC";
interrupt-parent = <&gic>;
#include "dt-bindings/clock/bcm281xx.h"
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "BCM11351 SoC";
compatible = "brcm,bcm11351";
interrupt-parent = <&gic>;
compatible = "brcm,bcm21664-garnet", "brcm,bcm21664";
memory {
+ device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
#include "dt-bindings/clock/bcm21664.h"
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "BCM21664 SoC";
compatible = "brcm,bcm21664";
interrupt-parent = <&gic>;
};
memory {
+ device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
};
/* BCM23550 and BCM21664 have almost identical clocks */
#include "dt-bindings/clock/bcm21664.h"
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "BCM23550 SoC";
compatible = "brcm,bcm23550";
interrupt-parent = <&gic>;
compatible = "brcm,bcm28155-ap", "brcm,bcm11351";
memory {
+ device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000>;
};
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
interrupt-parent = <&gic>;
chipcommonA {
};
memory@0 {
+ device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x68000000 0x08000000>;
};
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "brcm,bcm63138";
model = "Broadcom BCM63138 DSL SoC";
interrupt-parent = <&gic>;
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
-
/ {
#address-cells = <2>;
#size-cells = <2>;
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000>;
};
compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708";
memory {
+ device_type = "memory";
reg = <0x00000000 0x8000000>;
};
};
memory@80000000 {
+ device_type = "memory";
reg = <0x80000000 0x10000000>;
};
};
};
memory {
+ device_type = "memory";
reg = <0x80000000 0x10000000>;
};
};
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "cnxt,cx92755";
interrupt-parent = <&intc>;
// SPDX-License-Identifier: GPL-2.0
-/include/ "skeleton.dtsi"
-
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "marvell,dove";
model = "Marvell Armada 88AP510 SoC";
interrupt-parent = <&intc>;
/dts-v1/;
-#include "skeleton.dtsi"
-
#include <dt-bindings/clock/clps711x-clock.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Cirrus Logic EP7209";
compatible = "cirrus,ep7209";
compatible = "cirrus,edb7211", "cirrus,ep7211", "cirrus,ep7209";
memory {
+ device_type = "memory";
reg = <0xc0000000 0x02000000>;
};
* SoC core Device Tree for the ARM Integrator platforms
*/
-/include/ "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
core-module@10000000 {
compatible = "arm,core-module-integrator", "syscon", "simple-mfd";
reg = <0x10000000 0x200>;
// SPDX-License-Identifier: GPL-2.0
-/include/ "skeleton.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "marvell,kirkwood";
interrupt-parent = <&intc>;
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
-
#include <dt-bindings/clock/lpc32xx-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "nxp,lpc3220";
interrupt-parent = <&mic>;
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton64.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
compatible = "fsl,ls1021a";
interrupt-parent = <&gic>;
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x0>;
+ };
+
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-/include/ "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
interrupt-parent = <&gic>;
L2: l2-cache-controller@c4200000 {
};
memory {
+ device_type = "memory";
reg = <0x40000000 0x80000000>;
};
};
};
memory {
+ device_type = "memory";
reg = <0x40000000 0x80000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x40000000 0x40000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x40000000 0x40000000>;
};
};
};
memory {
+ device_type = "memory";
reg = <0x40000000 0x40000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x40000000 0x80000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x08000000>;
};
* publishhed by the Free Software Foundation.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/clock/marvell,mmp2.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
serial0 = &uart1;
serial1 = &uart2;
* Licensed under GPLv2 or later.
*/
-/include/ "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "moxa,moxart";
model = "MOXART";
interrupt-parent = <&intc>;
compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
memory {
+ device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/reset/mt2701-resets.h>
-#include "skeleton64.dtsi"
#include "mt2701-pinfunc.h"
/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
compatible = "mediatek,mt2701";
interrupt-parent = <&cirq>;
};
memory {
+ device_type = "memory";
reg = <0x80000000 0x20000000>;
};
};
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
/ {
compatible = "mediatek,mt6580";
};
memory {
+ device_type = "memory";
reg = <0x80000000 0x40000000>;
};
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "mediatek,mt6589";
interrupt-parent = <&sysirq>;
compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
memory {
+ device_type = "memory";
reg = <0x80000000 0x40000000>;
};
};
-
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "mediatek,mt6592";
interrupt-parent = <&sysirq>;
compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
memory {
+ device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
};
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton64.dtsi"
/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
compatible = "mediatek,mt8127";
interrupt-parent = <&sysirq>;
compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135";
memory {
+ device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
};
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/mt8135-resets.h>
-#include "skeleton64.dtsi"
#include "mt8135-pinfunc.h"
/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
compatible = "mediatek,mt8135";
interrupt-parent = <&sysirq>;
*
*/
-/include/ "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
interrupt-parent = <&intc>;
cpus {
compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x";
memory {
+ device_type = "memory";
reg = <0x00000000 0x4000000>; /* 64 MB */
};
compatible = "lacie,ethernet-disk-mini-v2", "marvell,orion5x-88f5182", "marvell,orion5x";
memory {
+ device_type = "memory";
reg = <0x00000000 0x4000000>; /* 64 MB */
};
compatible = "buffalo,lswsgl", "marvell,orion5x-88f5182", "marvell,orion5x";
memory {
+ device_type = "memory";
reg = <0x00000000 0x8000000>; /* 128 MB */
};
compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x";
memory {
+ device_type = "memory";
reg = <0x00000000 0x4000000>; /* 64 MB */
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x2000000>; /* 32 MB */
};
compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
memory {
+ device_type = "memory";
reg = <0x00000000 0x4000000>; /* 64 MB */
};
* warranty of any kind, whether express or implied.
*/
-#include "skeleton.dtsi"
-
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Marvell Orion5x SoC";
compatible = "marvell,orion5x";
interrupt-parent = <&intc>;
* Licensed under GPLv2 or later
*/
-/include/ "skeleton.dtsi"
#include <dt-bindings/clock/oxsemi,ox810se.h>
#include <dt-bindings/reset/oxsemi,ox810se.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "oxsemi,ox810se";
cpus {
};
memory {
+ device_type = "memory";
/* Max 256MB @ 0x48000000 */
reg = <0x48000000 0x10000000>;
};
* Licensed under GPLv2 or later
*/
-/include/ "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/oxsemi,ox820.h>
#include <dt-bindings/reset/oxsemi,ox820.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "oxsemi,ox820";
cpus {
};
memory {
+ device_type = "memory";
/* Max 512MB @ 0x60000000 */
reg = <0x60000000 0x20000000>;
};
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-/include/ "skeleton.dtsi"
/ {
model = "Picochip picoXcell PC3X2";
compatible = "picochip,pc3x2";
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-/include/ "skeleton.dtsi"
/ {
model = "Picochip picoXcell PC3X3";
compatible = "picochip,pc3x3";
compatible = "sirf,prima2", "sirf,prima2-cb";
memory {
+ device_type = "memory";
reg = <0x00000000 0x20000000>;
};
* Licensed under GPLv2 or later.
*/
-/include/ "skeleton.dtsi"
/ {
compatible = "sirf,prima2";
#address-cells = <1>;
* publishhed by the Free Software Foundation.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/clock/marvell,pxa168.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
serial0 = &uart1;
serial1 = &uart2;
* Licensed under GPLv2 or later.
*/
-#include "skeleton.dtsi"
#include "dt-bindings/clock/pxa-clock.h"
#define PMGROUP(pin) #pin
}
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Marvell PXA2xx family SoC";
compatible = "marvell,pxa2xx";
interrupt-parent = <&pxairq>;
* publishhed by the Free Software Foundation.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/clock/marvell,pxa910.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
serial0 = &uart1;
serial1 = &uart2;
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Qualcomm APQ8064";
compatible = "qcom,apq8064";
interrupt-parent = <&intc>;
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
thermal-zones {
cpu-thermal0 {
polling-delay-passive = <250>;
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-#include "skeleton.dtsi"
-
#include <dt-bindings/clock/qcom,gcc-apq8084.h>
#include <dt-bindings/gpio/gpio.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Qualcomm APQ 8084";
compatible = "qcom,apq8084";
interrupt-parent = <&intc>;
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
firmware {
scm {
compatible = "qcom,scm";
/dts-v1/;
-#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Qualcomm Technologies, Inc. IPQ4019";
compatible = "qcom,ipq4019";
interrupt-parent = <&intc>;
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Qualcomm IPQ8064";
compatible = "qcom,ipq8064";
interrupt-parent = <&intc>;
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
cpu-pmu {
compatible = "qcom,krait-pmu";
interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
compatible = "swir,wp8548", "qcom,mdm9615";
memory {
+ device_type = "memory";
reg = <0x48000000 0x7F00000>;
};
};
/dts-v1/;
-/include/ "skeleton.dtsi"
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-mdm9615.h>
#include <dt-bindings/reset/qcom,gcc-mdm9615.h>
#include <dt-bindings/soc/qcom,gsbi.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Qualcomm MDM9615";
compatible = "qcom,mdm9615";
interrupt-parent = <&intc>;
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-/include/ "skeleton.dtsi"
-
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8660.h>
#include <dt-bindings/soc/qcom,gsbi.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Qualcomm MSM8660";
compatible = "qcom,msm8660";
interrupt-parent = <&intc>;
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
cpu-pmu {
compatible = "qcom,scorpion-mp-pmu";
interrupts = <1 9 0x304>;
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-/include/ "skeleton.dtsi"
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/soc/qcom,gsbi.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Qualcomm MSM8960";
compatible = "qcom,msm8960";
interrupt-parent = <&intc>;
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
cpu-pmu {
compatible = "qcom,krait-pmu";
interrupts = <1 10 0x304>;
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/reset/qcom,gcc-msm8974.h>
#include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Qualcomm MSM8974";
compatible = "qcom,msm8974";
interrupt-parent = <&intc>;
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
thermal-zones {
cpu-thermal0 {
polling-delay-passive = <250>;
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Atmel SAMA5D2 family SoC";
compatible = "atmel,sama5d2";
interrupt-parent = <&aic>;
};
memory {
+ device_type = "memory";
reg = <0x20000000 0x20000000>;
};
* Licensed under GPLv2 or later.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Atmel SAMA5D3 family SoC";
compatible = "atmel,sama5d3", "atmel,sama5";
interrupt-parent = <&aic>;
};
memory {
+ device_type = "memory";
reg = <0x20000000 0x8000000>;
};
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/gpio/gpio.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
model = "Atmel SAMA5D4 family SoC";
compatible = "atmel,sama5d4";
interrupt-parent = <&aic>;
};
memory {
+ device_type = "memory";
reg = <0x20000000 0x20000000>;
};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * This file is deprecated, and will be removed once existing users have been
- * updated. New dts{,i} files should *not* include skeleton.dtsi, and should
- * instead explicitly provide the below nodes only as required.
- *
- * Skeleton device tree; the bare minimum needed to boot; just include and
- * add a compatible value. The bootloader will typically populate the memory
- * node.
- */
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- chosen { };
- aliases { };
- memory { device_type = "memory"; reg = <0 0>; };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Skeleton device tree in the 64 bits version; the bare minimum
- * needed to boot; just include and add a compatible value. The
- * bootloader will typically populate the memory node.
- */
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
- chosen { };
- aliases { };
- memory { device_type = "memory"; reg = <0 0 0 0>; };
-};
* http://www.gnu.org/copyleft/gpl.html
*/
-/include/ "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
* http://www.gnu.org/copyleft/gpl.html
*/
-/include/ "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
interrupt-parent = <&vic>;
cpus {
* http://www.gnu.org/copyleft/gpl.html
*/
-/include/ "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "st,spear600";
cpus {
*/
#include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
memory {
+ device_type = "memory";
reg = <0x00000000 0x04000000>,
<0x08000000 0x04000000>;
};
*/
/dts-v1/;
-/include/ "skeleton.dtsi"
/ {
model = "ST-Ericsson U300";
};
memory {
+ device_type = "memory";
reg = <0x48000000 0x03c00000>;
};
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x2000000>;
};
};
memory {
+ device_type = "memory";
reg = <0xc0000000 0x2000000>;
};
};
memory {
+ device_type = "memory";
reg = <0x90000000 0x800000>;
};
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/clock/stm32fx-clock.h>
#include <dt-bindings/mfd/stm32f4-rcc.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
};
memory {
+ device_type = "memory";
reg = <0x00000000 0x1000000>;
};
};
memory {
+ device_type = "memory";
reg = <0xC0000000 0x800000>;
};
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/clock/stm32fx-clock.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
};
memory {
+ device_type = "memory";
reg = <0xC0000000 0x1000000>;
};
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/clock/stm32h7-clks.h>
#include <dt-bindings/mfd/stm32h7-rcc.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
};
memory {
+ device_type = "memory";
reg = <0xd0000000 0x2000000>;
};
};
memory {
+ device_type = "memory";
reg = <0xd0000000 0x2000000>;
};
};
memory@c0000000 {
+ device_type = "memory";
reg = <0xC0000000 0x40000000>;
};
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-/include/ "skeleton.dtsi"
/ {
model = "ARM Versatile AB";
};
memory {
+ device_type = "memory";
reg = <0x0 0x08000000>;
};
* Licensed under GPLv2 or later
*/
-/include/ "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "via,vt8500";
cpus {
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
aliases {
serial0 = &uart0;
serial1 = &uart1;
* Licensed under GPLv2 or later
*/
-/include/ "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "wm,wm8505";
cpus {
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
aliases {
serial0 = &uart0;
serial1 = &uart1;
* Licensed under GPLv2 or later
*/
-/include/ "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "wm,wm8650";
cpus {
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
aliases {
serial0 = &uart0;
serial1 = &uart1;
* Licensed under GPLv2 or later
*/
-/include/ "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "wm,wm8750";
cpus {
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
aliases {
serial0 = &uart0;
serial1 = &uart1;
* Licensed under GPLv2 or later
*/
-/include/ "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "wm,wm8850";
cpus {
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
memory {
+ device_type = "memory";
reg = <0x50000000 0x20000000>;
};
};
// SPDX-License-Identifier: GPL-2.0
-#include "skeleton.dtsi"
#include <dt-bindings/clock/zx296702-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
git.samba.org / sfrench / cifs-2.6.git / commitdiff