x86, xsave: xsave cpuid feature bits
authorSuresh Siddha <suresh.b.siddha@intel.com>
Tue, 29 Jul 2008 17:29:18 +0000 (10:29 -0700)
committerIngo Molnar <mingo@elte.hu>
Wed, 30 Jul 2008 17:49:23 +0000 (19:49 +0200)
Add xsave CPU feature bits.

Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/feature_names.c
include/asm-x86/cpufeature.h

index 0bf4d37a04833e5b5532fa497453eb6410938130..741547225659ae992cfa3f835a413371dd27848a 100644 (file)
@@ -46,7 +46,7 @@ const char * const x86_cap_flags[NCAPINTS*32] = {
        "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
        "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
        NULL, NULL, "dca", "sse4_1", "sse4_2", "x2apic", NULL, "popcnt",
-       NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+       NULL, NULL, "xsave", NULL, NULL, NULL, NULL, NULL,
 
        /* VIA/Cyrix/Centaur-defined */
        NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
index 42afe9ca3a37e40cb0d2b172245b042e6fcde05f..c76b3f67cb3faa6e86380a674caba9a8afaffc68 100644 (file)
@@ -92,6 +92,7 @@
 #define X86_FEATURE_XTPR       (4*32+14) /* Send Task Priority Messages */
 #define X86_FEATURE_DCA                (4*32+18) /* Direct Cache Access */
 #define X86_FEATURE_X2APIC     (4*32+21) /* x2APIC */
+#define X86_FEATURE_XSAVE      (4*32+26) /* XSAVE */
 
 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
 #define X86_FEATURE_XSTORE     (5*32+ 2) /* on-CPU RNG present (xstore insn) */
@@ -191,6 +192,7 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_arch_perfmon   boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
 #define cpu_has_pat            boot_cpu_has(X86_FEATURE_PAT)
 #define cpu_has_x2apic         boot_cpu_has(X86_FEATURE_X2APIC)
+#define cpu_has_xsave          boot_cpu_has(X86_FEATURE_XSAVE)
 
 #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
 # define cpu_has_invlpg                1