Documentation: dt: socfpga: Add Arria10 NAND EDAC binding

Add the device tree bindings needed to support the Altera NAND FIFO
buffers on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1468512408-5156-2-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index b545856a444fe929078b7f84ce75537ce8e7485f..1bcbab216294239f441328daca703884639bfb11 100644 (file)
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -90,6 +90,14 @@ Required Properties:
 - interrupts      : Should be single bit error interrupt, then double bit error
        interrupt, in this order.
 
+NAND FIFO ECC
+Required Properties:
+- compatible      : Should be "altr,socfpga-nand-ecc"
+- reg             : Address and size for ECC block registers.
+- altr,ecc-parent : phandle to parent NAND node.
+- interrupts      : Should be single bit error interrupt, then double bit error
+       interrupt, in this order.
+
 Example:
 
        eccmgr: eccmgr@ffd06000 {
@@ -132,4 +140,28 @@ Example:
                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
                                     <37 IRQ_TYPE_LEVEL_HIGH>;
                };
+
+               nand-buf-ecc@ff8c2000 {
+                       compatible = "altr,socfpga-nand-ecc";
+                       reg = <0xff8c2000 0x400>;
+                       altr,ecc-parent = <&nand>;
+                       interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
+                                    <43 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               nand-rd-ecc@ff8c2400 {
+                       compatible = "altr,socfpga-nand-ecc";
+                       reg = <0xff8c2400 0x400>;
+                       altr,ecc-parent = <&nand>;
+                       interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
+                                    <45 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               nand-wr-ecc@ff8c2800 {
+                       compatible = "altr,socfpga-nand-ecc";
+                       reg = <0xff8c2800 0x400>;
+                       altr,ecc-parent = <&nand>;
+                       interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+                                    <44 IRQ_TYPE_LEVEL_HIGH>;
+               };
        };