arm64: cpufeature: expose arm64_ftr_reg struct for CTR_EL0
authorArd Biesheuvel <ard.biesheuvel@linaro.org>
Wed, 31 Aug 2016 10:31:10 +0000 (11:31 +0100)
committerWill Deacon <will.deacon@arm.com>
Wed, 31 Aug 2016 12:48:15 +0000 (13:48 +0100)
Expose the arm64_ftr_reg struct covering CTR_EL0 outside of cpufeature.o
so that other code can refer to it directly (i.e., without performing the
binary search)

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
arch/arm64/include/asm/cpufeature.h
arch/arm64/kernel/cpufeature.c

index 8bb4f1527b269de09d9bf72233e05fc2f4fb8aa5..c07c5d1cd04ac53852a55b989d89753f9f2f45cd 100644 (file)
@@ -78,6 +78,8 @@ struct arm64_ftr_reg {
        const struct arm64_ftr_bits     *ftr_bits;
 };
 
+extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
+
 /* scope of capability check */
 enum {
        SCOPE_SYSTEM,
index cc7451a27d94e18f30096ac85485571eb2617408..c3d7ae48f92dcb144fdd399b305211d0d1c50b63 100644 (file)
@@ -155,6 +155,11 @@ static const struct arm64_ftr_bits ftr_ctr[] = {
        ARM64_FTR_END,
 };
 
+struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
+       .name           = "SYS_CTR_EL0",
+       .ftr_bits       = ftr_ctr
+};
+
 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
        S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf),    /* InnerShr */
        ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),        /* FCSE */
@@ -318,7 +323,7 @@ static const struct __ftr_reg_entry {
        ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 
        /* Op1 = 3, CRn = 0, CRm = 0 */
-       ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
+       { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
        ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 
        /* Op1 = 3, CRn = 14, CRm = 0 */