RISC-V: Enable sstc extension parsing from DT
authorAtish Patra <atishp@rivosinc.com>
Fri, 22 Jul 2022 16:50:45 +0000 (09:50 -0700)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 11 Aug 2022 21:36:13 +0000 (14:36 -0700)
The ISA extension framework now allows parsing any multi-letter
ISA extension.

Enable that for sstc extension.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20220722165047.519994-3-atishp@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/hwcap.h
arch/riscv/kernel/cpu.c
arch/riscv/kernel/cpufeature.c

index 4e24868818408d001844dd2f16507bafcb091369..b186fff75198ceaf16de8544c1e793c52ee5e882 100644 (file)
@@ -53,6 +53,7 @@ extern unsigned long elf_hwcap;
 enum riscv_isa_ext_id {
        RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
        RISCV_ISA_EXT_SVPBMT,
+       RISCV_ISA_EXT_SSTC,
        RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
 };
 
index fba9e9f46a8c7aa4cc54c681341caaab368f9f1a..0016d9337fe09b7ff173da4906c494b5283173af 100644 (file)
@@ -89,6 +89,7 @@ int riscv_of_parent_hartid(struct device_node *node)
 static struct riscv_isa_ext_data isa_ext_arr[] = {
        __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
        __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
+       __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
        __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
 };
 
index a6f62a6d1edd92ca1cade5fd802daf718b08f35c..d1d83cd9fd4bb790393ac331835909b86bd704d9 100644 (file)
@@ -199,6 +199,7 @@ void __init riscv_fill_hwcap(void)
                        } else {
                                SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
                                SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
+                               SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
                        }
 #undef SET_ISA_EXT_MAP
                }