Merge branch 'pci/misc' into next
authorBjorn Helgaas <bhelgaas@google.com>
Wed, 31 Jan 2018 16:10:32 +0000 (10:10 -0600)
committerBjorn Helgaas <helgaas@kernel.org>
Wed, 31 Jan 2018 16:10:32 +0000 (10:10 -0600)
* pci/misc:
  PCI: Add dummy pci_irqd_intx_xlate() for CONFIG_PCI=n build
  PCI: Add wrappers for dev_printk()
  PCI: Remove unnecessary messages for memory allocation failures
  PCI: Add #defines for Completion Timeout Disable feature
  hinic: Replace PCI pool old API
  net: e100: Replace PCI pool old API
  block: DAC960: Replace PCI pool old API
  MAINTAINERS: Include more PCI files
  PCI: Remove unneeded kallsyms include
  powerpc/pci: Unroll two pass loop when scanning bridges
  powerpc/pci: Use for_each_pci_bridge() helper

1  2 
drivers/pci/hotplug/ibmphp_core.c
drivers/pci/hotplug/pciehp_hpc.c
drivers/pci/pci.c
drivers/pci/pcie/aer/aerdrv_core.c
drivers/pci/pcie/aspm.c
drivers/pci/probe.c
drivers/pci/quirks.c
drivers/pci/xen-pcifront.c
include/linux/pci.h
include/uapi/linux/pci_regs.h

Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
index 24e9a148e7346c516995a270470fed4885ebdf01,e5cccc64940c8ecbd7ae61ab900f671cec020c34..78047dc892139348b3e5fef0300ce163480fb4f9
@@@ -2699,10 -2696,9 +2696,10 @@@ static void __nv_msi_ht_cap_quirk(struc
         * HT MSI mapping should be disabled on devices that are below
         * a non-Hypertransport host bridge. Locate the host bridge...
         */
 -      host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 +      host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
 +                                                PCI_DEVFN(0, 0));
        if (host_bridge == NULL) {
-               dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
+               pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
                return;
        }
  
Simple merge
Simple merge
index c8586db4fb07b61e5ad44fb3e247efb0c6386959,9dc67643fc180af3a71b3776c3808f0457f0917b..0c79eac5e9b8ef00deb54bf61bd7004207aabeb1
   * safely.
   */
  #define PCI_EXP_DEVCAP2               36      /* Device Capabilities 2 */
+ #define  PCI_EXP_DEVCAP2_COMP_TMOUT_DIS       0x00000010 /* Completion Timeout Disable supported */
  #define  PCI_EXP_DEVCAP2_ARI          0x00000020 /* Alternative Routing-ID */
  #define  PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */
 -#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* Atomic 64-bit compare */
 +#define  PCI_EXP_DEVCAP2_ATOMIC_COMP32        0x00000080 /* 32b AtomicOp completion */
 +#define  PCI_EXP_DEVCAP2_ATOMIC_COMP64        0x00000100 /* 64b AtomicOp completion */
 +#define  PCI_EXP_DEVCAP2_ATOMIC_COMP128       0x00000200 /* 128b AtomicOp completion */
  #define  PCI_EXP_DEVCAP2_LTR          0x00000800 /* Latency tolerance reporting */
  #define  PCI_EXP_DEVCAP2_OBFF_MASK    0x000c0000 /* OBFF support mechanism */
  #define  PCI_EXP_DEVCAP2_OBFF_MSG     0x00040000 /* New message signaling */