clk: imx6q: add mmdc0 ipg clock
authorAnson Huang <Anson.Huang@nxp.com>
Fri, 31 Aug 2018 07:53:17 +0000 (15:53 +0800)
committerStephen Boyd <sboyd@kernel.org>
Wed, 17 Oct 2018 18:16:02 +0000 (11:16 -0700)
i.MX6Q has MMDC0 ipg clock in CCM CCGR, add it into
clock tree for clock management.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/imx/clk-imx6q.c
include/dt-bindings/clock/imx6qdl-clock.h

index 8c7c2fcb8d9495a6597fa7020d3b297278ec961e..bbe0c60f4d09f868a0a5c7d5cca22d72e66e0013 100644 (file)
@@ -789,6 +789,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb",            "axi",               base + 0x74, 18);
        clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2_flags("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20, CLK_IS_CRITICAL);
        clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
+       clk[IMX6QDL_CLK_MMDC_P0_IPG]  = imx_clk_gate2_flags("mmdc_p0_ipg",   "ipg",         base + 0x74, 24, CLK_IS_CRITICAL);
        clk[IMX6QDL_CLK_OCRAM]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
        clk[IMX6QDL_CLK_OPENVG_AXI]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
        clk[IMX6QDL_CLK_PCIE_AXI]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
index 7ad171b8f3bfc0e7e72b67083e7110a5fee4d02c..87b068f4a9982785e30f80e23c2c33952fd17bb9 100644 (file)
 #define IMX6QDL_CLK_MLB_PODF                   260
 #define IMX6QDL_CLK_EPIT1                      261
 #define IMX6QDL_CLK_EPIT2                      262
-#define IMX6QDL_CLK_END                                263
+#define IMX6QDL_CLK_MMDC_P0_IPG                        263
+#define IMX6QDL_CLK_END                                264
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */