rtw89: pci: add deglitch setting
authorPing-Ke Shih <pkshih@realtek.com>
Fri, 25 Mar 2022 06:00:45 +0000 (14:00 +0800)
committerKalle Valo <kvalo@kernel.org>
Wed, 6 Apr 2022 08:55:13 +0000 (11:55 +0300)
Add setting to support 8852ce.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220325060055.58482-7-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/pci.c
drivers/net/wireless/realtek/rtw89/pci.h

index 25d385be6e862836ec481cb4246def80753ddb1e..5112b2d443c3eb52b5a529611b86c8461cf2b775 100644 (file)
@@ -1809,19 +1809,24 @@ end:
 
 static int rtw89_pci_deglitch_setting(struct rtw89_dev *rtwdev)
 {
+       enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
        int ret;
 
-       if (rtwdev->chip->chip_id != RTL8852A)
-               return 0;
-
-       ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH,
-                                    PCIE_PHY_GEN1);
-       if (ret)
-               return ret;
-       ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH,
-                                    PCIE_PHY_GEN2);
-       if (ret)
-               return ret;
+       if (chip_id == RTL8852A) {
+               ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH,
+                                            PCIE_PHY_GEN1);
+               if (ret)
+                       return ret;
+               ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH,
+                                            PCIE_PHY_GEN2);
+               if (ret)
+                       return ret;
+       } else if (chip_id == RTL8852C) {
+               rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_G1 + RAC_ANA24 * 2,
+                                 B_AX_DEGLITCH);
+               rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_G2 + RAC_ANA24 * 2,
+                                 B_AX_DEGLITCH);
+       }
 
        return 0;
 }
index 99f0cd2f47da29f2a99b9069458228d402408deb..805fc3e8c1a4a5e446e6726275884ef38800dd4f 100644 (file)
@@ -80,6 +80,9 @@
 #define R_AX_PCIE_WDT_TIMER_S1 0x3128
 #define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)
 
+#define R_RAC_DIRECT_OFFSET_G1 0x3800
+#define R_RAC_DIRECT_OFFSET_G2 0x3880
+
 #define RTW89_PCI_WR_RETRY_CNT         20
 
 /* Interrupts */