mfd: imx6sx: Add MQS register definition for iomuxc gpr

Add macros to define masks and bits for imx6sx MQS registers

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index c1b25f5e386d55e12545d1d958dc119cba7eb2dc..f232c8130d00e47bd9907edb31a866beafae04c4 100644 (file)
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -410,6 +410,15 @@
 #define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK             (0x3 << 17)
 #define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT              (0x3 << 13)
 
+#define IMX6SX_GPR2_MQS_OVERSAMPLE_MASK                        (0x1 << 26)
+#define IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT               (26)
+#define IMX6SX_GPR2_MQS_EN_MASK                                (0x1 << 25)
+#define IMX6SX_GPR2_MQS_EN_SHIFT                       (25)
+#define IMX6SX_GPR2_MQS_SW_RST_MASK                    (0x1 << 24)
+#define IMX6SX_GPR2_MQS_SW_RST_SHIFT                   (24)
+#define IMX6SX_GPR2_MQS_CLK_DIV_MASK                   (0xFF << 16)
+#define IMX6SX_GPR2_MQS_CLK_DIV_SHIFT                  (16)
+
 #define IMX6SX_GPR4_FEC_ENET1_STOP_REQ                 (0x1 << 3)
 #define IMX6SX_GPR4_FEC_ENET2_STOP_REQ                 (0x1 << 4)