arm64/perf: Define complete ARMv8 recommended implementation defined events

Defined all the ARMv8 recommended implementation defined events
from J3 - "ARM recommendations for IMPLEMENTATION DEFINED event numbers"
in ARM DDI 0487A.g.

Signed-off-by: Ashok Kumar <ashoks@broadcom.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 5dcdbffa28e7e47540e90727927fb9c44488c2b9..d5a02bc756674910f41426014f5c04fe9874b78a 100644 (file)
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -94,10 +94,89 @@
 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR                      0x41
 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD               0x42
 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR               0x43
+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER            0x44
+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER            0x45
+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM               0x46
+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN                        0x47
+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL                   0x48
+
 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD                 0x4C
 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR                 0x4D
 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD                                0x4E
 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR                                0x4F
+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD                      0x50
+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR                      0x51
+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD               0x52
+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR               0x53
+
+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM               0x56
+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN                        0x57
+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL                   0x58
+
+#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD                 0x5C
+#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR                 0x5D
+#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD                                0x5E
+#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR                                0x5F
+
+#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD                     0x60
+#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR                     0x61
+#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED                 0x62
+#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED             0x63
+#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL                 0x64
+#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH                 0x65
+
+#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD                     0x66
+#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR                     0x67
+#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC                 0x68
+#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC                 0x69
+#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC               0x6A
+
+#define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC                                0x6C
+#define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC                   0x6D
+#define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC                   0x6E
+#define ARMV8_IMPDEF_PERFCTR_STREX_SPEC                                0x6F
+#define ARMV8_IMPDEF_PERFCTR_LD_SPEC                           0x70
+#define ARMV8_IMPDEF_PERFCTR_ST_SPEC                           0x71
+#define ARMV8_IMPDEF_PERFCTR_LDST_SPEC                         0x72
+#define ARMV8_IMPDEF_PERFCTR_DP_SPEC                           0x73
+#define ARMV8_IMPDEF_PERFCTR_ASE_SPEC                          0x74
+#define ARMV8_IMPDEF_PERFCTR_VFP_SPEC                          0x75
+#define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC                     0x76
+#define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC                       0x77
+#define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC                     0x78
+#define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC                    0x79
+#define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC                  0x7A
+
+#define ARMV8_IMPDEF_PERFCTR_ISB_SPEC                          0x7C
+#define ARMV8_IMPDEF_PERFCTR_DSB_SPEC                          0x7D
+#define ARMV8_IMPDEF_PERFCTR_DMB_SPEC                          0x7E
+
+#define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF                         0x81
+#define ARMV8_IMPDEF_PERFCTR_EXC_SVC                           0x82
+#define ARMV8_IMPDEF_PERFCTR_EXC_PABORT                                0x83
+#define ARMV8_IMPDEF_PERFCTR_EXC_DABORT                                0x84
+
+#define ARMV8_IMPDEF_PERFCTR_EXC_IRQ                           0x86
+#define ARMV8_IMPDEF_PERFCTR_EXC_FIQ                           0x87
+#define ARMV8_IMPDEF_PERFCTR_EXC_SMC                           0x88
+
+#define ARMV8_IMPDEF_PERFCTR_EXC_HVC                           0x8A
+#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT                   0x8B
+#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT                   0x8C
+#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER                    0x8D
+#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ                      0x8E
+#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ                      0x8F
+#define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC                                0x90
+#define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC                                0x91
+
+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD                      0xA0
+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR                      0xA1
+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD               0xA2
+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR               0xA3
+
+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM               0xA6
+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN                        0xA7
+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL                   0xA8
 
 /* ARMv8 Cortex-A53 specific event types. */
 #define ARMV8_A53_PERFCTR_PREF_LINEFILL                                0xC2