drm/amd/display: Update driver and IPS interop
authorDuncan Ma <duncan.ma@amd.com>
Wed, 16 Aug 2023 16:28:05 +0000 (12:28 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 20 Sep 2023 20:24:08 +0000 (16:24 -0400)
commitdc01c4b79bfe052ef0f9624b5e6ea9b05347f5f0
treef66afb27b8da30cd7661a54a008b04049f72132d
parent4f43d753bf9c709ff771eb6dff76269e657555a6
drm/amd/display: Update driver and IPS interop

[Why]
Two issues fixed:

1. Currently, driver does not allow idle prior to PSR entry. Once
   PSR1+IPS is enabled, there is intermittent hang due to DCN access
from IrqMgr during IPS2.

2. Driver is sending multiple commands to PMFW and dmcub to exit IPS
   even during IPS0.

[How]
1. Set driver allow optimization prior to entering PSR mode with the
   condition for eDP display only.  Unregister all interrupts before
   allowing driver idle and re-register interrupts when exiting from
   idle. This will prevent IrqMgr to access DCN during IPS2.

2. Block sending PMFW and dmcub exit low power state commands when
   driver is not in idle state.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c