clk: qoriq: add more PLL divider clocks support
authorYuantian Tang <andy.tang@nxp.com>
Mon, 22 Apr 2019 09:15:09 +0000 (17:15 +0800)
committerStephen Boyd <sboyd@kernel.org>
Thu, 25 Apr 2019 18:22:46 +0000 (11:22 -0700)
commitcc61ab9ba2da6587d2b8acfa9d3cf3900456d3b6
tree0d057a93a236c40d8d8256c062f31b56b15de628
parentf34b2c26fc7d120b26cb181b8d4115675ec58244
clk: qoriq: add more PLL divider clocks support

More PLL divider clocks are needed by clock consumer IP. So enlarge
the PLL divider array to accommodate more divider clocks.

Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/clk-qoriq.c