csky: Revert mmu ASID mechanism
authorGuo Ren <ren_guo@c-sky.com>
Tue, 18 Jun 2019 09:20:10 +0000 (17:20 +0800)
committerGuo Ren <ren_guo@c-sky.com>
Fri, 19 Jul 2019 06:21:36 +0000 (14:21 +0800)
commit9d35dc3006a9865eb5b55cc79df49933601131f8
tree6f16dbd7f5111bcea394079e199bb68701459235
parent4d581034f9086f784a3408575bdb3c201740c6cb
csky: Revert mmu ASID mechanism

Current C-SKY ASID mechanism is from mips and it doesn't work well
with multi-cores. ASID per core mechanism is not suitable for C-SKY
SMP tlb maintain operations, eg: tlbi.vas need share the same asid
in all processors and it'll invalid the tlb entry in all cores with
the same asid.

This patch is prepare for new ASID mechanism.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
arch/csky/include/asm/mmu.h
arch/csky/include/asm/mmu_context.h
arch/csky/include/asm/pgtable.h
arch/csky/kernel/smp.c
arch/csky/mm/init.c
arch/csky/mm/tlb.c