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(parent: 3c317d0) | patch
ARM: MM: Add DT binding for Feroceon L2 cache
authorAndrew Lunn <andrew@lunn.ch>
Sat, 22 Feb 2014 19:14:52 +0000 (20:14 +0100)
committerJason Cooper <jason@lakedaemon.net>
Sat, 22 Feb 2014 20:43:49 +0000 (20:43 +0000)
commit4b8f7a11c9fb680895e5079788653a59d6bdde16
treed20f78bd55eb043f8f9e1be5e702301263b73079tree
parent3c317d00ba4a9489c161857a574432c61fde4a2acommit | diff
ARM: MM: Add DT binding for Feroceon L2 cache

Instantiate the L2 cache from DT. Indicate in DT where the cache
control register is so that it is possible to enable/disable write
through on the CPU.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Documentation/devicetree/bindings/arm/mrvl/feroceon.txt [new file with mode: 0644] blob
arch/arm/include/asm/hardware/cache-feroceon-l2.h diff | blob | history
arch/arm/mach-kirkwood/board-dt.c diff | blob | history
arch/arm/mm/cache-feroceon-l2.c diff | blob | history
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