Merge branches 'work.misc' and 'work.dcache' of git://git.kernel.org/pub/scm/linux...

[sfrench/cifs-2.6.git] / tools / perf / pmu-events / arch / s390 / cf_z10 / extended.json

diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/extended.json b/tools/perf/pmu-events/arch/s390/cf_z10/extended.json
index 0feedb40f30f46f0712c41c853965898af3174d2..b6b7f29ca831c6463920887c64ad589cbd41ffca 100644 (file)
--- a/tools/perf/pmu-events/arch/s390/cf_z10/extended.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z10/extended.json
@@ -1,107 +1,125 @@
 [
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "128",
                "EventName": "L1I_L2_SOURCED_WRITES",
                "BriefDescription": "L1I L2 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "129",
                "EventName": "L1D_L2_SOURCED_WRITES",
                "BriefDescription": "L1D L2 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "130",
                "EventName": "L1I_L3_LOCAL_WRITES",
                "BriefDescription": "L1I L3 Local Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "131",
                "EventName": "L1D_L3_LOCAL_WRITES",
                "BriefDescription": "L1D L3 Local Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "132",
                "EventName": "L1I_L3_REMOTE_WRITES",
                "BriefDescription": "L1I L3 Remote Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "133",
                "EventName": "L1D_L3_REMOTE_WRITES",
                "BriefDescription": "L1D L3 Remote Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "134",
                "EventName": "L1D_LMEM_SOURCED_WRITES",
                "BriefDescription": "L1D Local Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "135",
                "EventName": "L1I_LMEM_SOURCED_WRITES",
                "BriefDescription": "L1I Local Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "136",
                "EventName": "L1D_RO_EXCL_WRITES",
                "BriefDescription": "L1D Read-only Exclusive Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "137",
                "EventName": "L1I_CACHELINE_INVALIDATES",
                "BriefDescription": "L1I Cacheline Invalidates",
                "PublicDescription": "A cache line in the Level-1 I-Cache has been invalidated by a store on the same CPU as the Level-1 I-Cache"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "138",
                "EventName": "ITLB1_WRITES",
                "BriefDescription": "ITLB1 Writes",
                "PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "139",
                "EventName": "DTLB1_WRITES",
                "BriefDescription": "DTLB1 Writes",
                "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "140",
                "EventName": "TLB2_PTE_WRITES",
                "BriefDescription": "TLB2 PTE Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "141",
                "EventName": "TLB2_CRSTE_WRITES",
                "BriefDescription": "TLB2 CRSTE Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "142",
                "EventName": "TLB2_CRSTE_HPAGE_WRITES",
                "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "145",
                "EventName": "ITLB1_MISSES",
                "BriefDescription": "ITLB1 Misses",
                "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "146",
                "EventName": "DTLB1_MISSES",
                "BriefDescription": "DTLB1 Misses",
                "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress"
        },
        {
+               "Unit": "CPU-M-CF",
                "EventCode": "147",
                "EventName": "L2C_STORES_SENT",
                "BriefDescription": "L2C Stores Sent",