Merge branches 'work.misc' and 'work.dcache' of git://git.kernel.org/pub/scm/linux...

[sfrench/cifs-2.6.git] / tools / memory-model / Documentation / recipes.txt

diff --git a/tools/memory-model/Documentation/recipes.txt b/tools/memory-model/Documentation/recipes.txt
index ee4309a87fc45b625581a9478e69c547b6e9e1ef..af72700cc20a20ca8d8d2d524c1d777dd9c1e988 100644 (file)
--- a/tools/memory-model/Documentation/recipes.txt
+++ b/tools/memory-model/Documentation/recipes.txt
@@ -126,7 +126,7 @@ However, it is not necessarily the case that accesses ordered by
 locking will be seen as ordered by CPUs not holding that lock.
 Consider this example:
 
-       /* See Z6.0+pooncelock+pooncelock+pombonce.litmus. */
+       /* See Z6.0+pooncerelease+poacquirerelease+fencembonceonce.litmus. */
        void CPU0(void)
        {
                spin_lock(&mylock);
@@ -292,7 +292,7 @@ and to use smp_load_acquire() instead of smp_rmb().  However, the older
 smp_wmb() and smp_rmb() APIs are still heavily used, so it is important
 to understand their use cases.  The general approach is shown below:
 
-       /* See MP+wmbonceonce+rmbonceonce.litmus. */
+       /* See MP+fencewmbonceonce+fencermbonceonce.litmus. */
        void CPU0(void)
        {
                WRITE_ONCE(x, 1);
@@ -322,9 +322,9 @@ the following write-side code fragment:
 And the xlog_valid_lsn() function in fs/xfs/xfs_log_priv.h contains
 the corresponding read-side code fragment:
 
-       cur_cycle = ACCESS_ONCE(log->l_curr_cycle);
+       cur_cycle = READ_ONCE(log->l_curr_cycle);
        smp_rmb();
-       cur_block = ACCESS_ONCE(log->l_curr_block);
+       cur_block = READ_ONCE(log->l_curr_block);
 
 Alternatively, consider the following comment in function
 perf_output_put_handle() in kernel/events/ring_buffer.c:
@@ -360,7 +360,7 @@ can be seen in the LB+poonceonces.litmus litmus test.
 One way of avoiding the counter-intuitive outcome is through the use of a
 control dependency paired with a full memory barrier:
 
-       /* See LB+ctrlonceonce+mbonceonce.litmus. */
+       /* See LB+fencembonceonce+ctrlonceonce.litmus. */
        void CPU0(void)
        {
                r0 = READ_ONCE(x);
@@ -476,7 +476,7 @@ that one CPU first stores to one variable and then loads from a second,
 while another CPU stores to the second variable and then loads from the
 first.  Preserving order requires nothing less than full barriers:
 
-       /* See SB+mbonceonces.litmus. */
+       /* See SB+fencembonceonces.litmus. */
        void CPU0(void)
        {
                WRITE_ONCE(x, 1);