Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

[sfrench/cifs-2.6.git] / include / asm-mips / mipsregs.h

diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 9985cb7c16e726e22f90ef58f50692920c73ced6..aa17f658f73c9d164036fb838554f6e8ec1dc572 100644 (file)
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -7,7 +7,7 @@
  * Copyright (C) 2000 Silicon Graphics, Inc.
  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  */
 #ifndef _ASM_MIPSREGS_H
@@ -15,6 +15,7 @@
 
 #include <linux/linkage.h>
 #include <asm/hazards.h>
+#include <asm/war.h>
 
 /*
  * The following macros are especially useful for __asm__
@@ -533,6 +534,12 @@
 #define MIPS_CONF3_VEIC                (_ULCAST_(1) <<  6)
 #define MIPS_CONF3_LPA         (_ULCAST_(1) <<  7)
 #define MIPS_CONF3_DSP         (_ULCAST_(1) << 10)
+#define MIPS_CONF3_ULRI                (_ULCAST_(1) << 13)
+
+#define MIPS_CONF7_WII         (_ULCAST_(1) << 31)
+
+#define MIPS_CONF7_RPS         (_ULCAST_(1) << 2)
+
 
 /*
  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
@@ -700,10 +707,10 @@ do {                                                                      \
  */
 #define __read_64bit_c0_split(source, sel)                             \
 ({                                                                     \
-       unsigned long long val;                                         \
-       unsigned long flags;                                            \
+       unsigned long long __val;                                       \
+       unsigned long __flags;                                          \
                                                                        \
-       local_irq_save(flags);                                          \
+       local_irq_save(__flags);                                        \
        if (sel == 0)                                                   \
                __asm__ __volatile__(                                   \
                        ".set\tmips64\n\t"                              \
@@ -712,7 +719,7 @@ do {                                                                        \
                        "dsrl\t%M0, %M0, 32\n\t"                        \
                        "dsrl\t%L0, %L0, 32\n\t"                        \
                        ".set\tmips0"                                   \
-                       : "=r" (val));                                  \
+                       : "=r" (__val));                                \
        else                                                            \
                __asm__ __volatile__(                                   \
                        ".set\tmips64\n\t"                              \
@@ -721,17 +728,17 @@ do {                                                                      \
                        "dsrl\t%M0, %M0, 32\n\t"                        \
                        "dsrl\t%L0, %L0, 32\n\t"                        \
                        ".set\tmips0"                                   \
-                       : "=r" (val));                                  \
-       local_irq_restore(flags);                                       \
+                       : "=r" (__val));                                \
+       local_irq_restore(__flags);                                     \
                                                                        \
-       val;                                                            \
+       __val;                                                          \
 })
 
 #define __write_64bit_c0_split(source, sel, val)                       \
 do {                                                                   \
-       unsigned long flags;                                            \
+       unsigned long __flags;                                          \
                                                                        \
-       local_irq_save(flags);                                          \
+       local_irq_save(__flags);                                        \
        if (sel == 0)                                                   \
                __asm__ __volatile__(                                   \
                        ".set\tmips64\n\t"                              \
@@ -752,7 +759,7 @@ do {                                                                        \
                        "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
                        ".set\tmips0"                                   \
                        : : "r" (val));                                 \
-       local_irq_restore(flags);                                       \
+       local_irq_restore(__flags);                                     \
 } while (0)
 
 #define read_c0_index()                __read_32bit_c0_register($0, 0)
@@ -770,6 +777,9 @@ do {                                                                        \
 #define read_c0_context()      __read_ulong_c0_register($4, 0)
 #define write_c0_context(val)  __write_ulong_c0_register($4, 0, val)
 
+#define read_c0_userlocal()    __read_ulong_c0_register($4, 2)
+#define write_c0_userlocal(val)        __write_ulong_c0_register($4, 2, val)
+
 #define read_c0_pagemask()     __read_32bit_c0_register($5, 0)
 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
 
@@ -971,7 +981,7 @@ do {                                                                        \
 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
 
 /* MIPSR2 */
-#define read_c0_hwrena()       __read_32bit_c0_register($7,0)
+#define read_c0_hwrena()       __read_32bit_c0_register($7, 0)
 #define write_c0_hwrena(val)   __write_32bit_c0_register($7, 0, val)
 
 #define read_c0_intctl()       __read_32bit_c0_register($12, 1)
@@ -983,7 +993,7 @@ do {                                                                        \
 #define read_c0_srsmap()       __read_32bit_c0_register($12, 3)
 #define write_c0_srsmap(val)   __write_32bit_c0_register($12, 3, val)
 
-#define read_c0_ebase()                __read_32bit_c0_register($15,1)
+#define read_c0_ebase()                __read_32bit_c0_register($15, 1)
 #define write_c0_ebase(val)    __write_32bit_c0_register($15, 1, val)
 
 /*
@@ -1292,10 +1302,39 @@ static inline void tlb_probe(void)
 
 static inline void tlb_read(void)
 {
+#if MIPS34K_MISSED_ITLB_WAR
+       int res = 0;
+
+       __asm__ __volatile__(
+       "       .set    push                                    \n"
+       "       .set    noreorder                               \n"
+       "       .set    noat                                    \n"
+       "       .set    mips32r2                                \n"
+       "       .word   0x41610001              # dvpe $1       \n"
+       "       move    %0, $1                                  \n"
+       "       ehb                                             \n"
+       "       .set    pop                                     \n"
+       : "=r" (res));
+
+       instruction_hazard();
+#endif
+
        __asm__ __volatile__(
                ".set noreorder\n\t"
                "tlbr\n\t"
                ".set reorder");
+
+#if MIPS34K_MISSED_ITLB_WAR
+       if ((res & _ULCAST_(1)))
+               __asm__ __volatile__(
+               "       .set    push                            \n"
+               "       .set    noreorder                       \n"
+               "       .set    noat                            \n"
+               "       .set    mips32r2                        \n"
+               "       .word   0x41600021      # evpe          \n"
+               "       ehb                                     \n"
+               "       .set    pop                             \n");
+#endif
 }
 
 static inline void tlb_write_indexed(void)