Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi

[sfrench/cifs-2.6.git] / drivers / scsi / ufs / ufs-qcom.c

diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
index a6b6f6eb9061aa7953db98a68e2cda63966c4dcb..ea7219407309eaafabdfb070bc5f9828725c51fb 100644 (file)
--- a/drivers/scsi/ufs/ufs-qcom.c
+++ b/drivers/scsi/ufs/ufs-qcom.c
@@ -16,6 +16,7 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/phy/phy.h>
+#include <linux/reset-controller.h>
 
 #include "ufshcd.h"
 #include "ufshcd-pltfrm.h"
@@ -49,6 +50,11 @@ static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
                                                       u32 clk_cycles);
 
+static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
+{
+       return container_of(rcd, struct ufs_qcom_host, rcdev);
+}
+
 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
                                       const char *prefix, void *priv)
 {
@@ -255,11 +261,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
        if (is_rate_B)
                phy_set_mode(phy, PHY_MODE_UFS_HS_B);
 
-       /* Assert PHY reset and apply PHY calibration values */
-       ufs_qcom_assert_reset(hba);
-       /* provide 1ms delay to let the reset pulse propagate */
-       usleep_range(1000, 1100);
-
        /* phy initialization - calibrate the phy */
        ret = phy_init(phy);
        if (ret) {
@@ -268,15 +269,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
                goto out;
        }
 
-       /* De-assert PHY reset and start serdes */
-       ufs_qcom_deassert_reset(hba);
-
-       /*
-        * after reset deassertion, phy will need all ref clocks,
-        * voltage, current to settle down before starting serdes.
-        */
-       usleep_range(1000, 1100);
-
        /* power on phy - start serdes and phy's power and clocks */
        ret = phy_power_on(phy);
        if (ret) {
@@ -290,7 +282,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
        return 0;
 
 out_disable_phy:
-       ufs_qcom_assert_reset(hba);
        phy_exit(phy);
 out:
        return ret;
@@ -554,21 +545,10 @@ static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
                ufs_qcom_disable_lane_clks(host);
                phy_power_off(phy);
 
-               /* Assert PHY soft reset */
-               ufs_qcom_assert_reset(hba);
-               goto out;
-       }
-
-       /*
-        * If UniPro link is not active, PHY ref_clk, main PHY analog power
-        * rail and low noise analog power rail for PLL can be switched off.
-        */
-       if (!ufs_qcom_is_link_active(hba)) {
+       } else if (!ufs_qcom_is_link_active(hba)) {
                ufs_qcom_disable_lane_clks(host);
-               phy_power_off(phy);
        }
 
-out:
        return ret;
 }
 
@@ -578,21 +558,26 @@ static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
        struct phy *phy = host->generic_phy;
        int err;
 
-       err = phy_power_on(phy);
-       if (err) {
-               dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
-                       __func__, err);
-               goto out;
-       }
+       if (ufs_qcom_is_link_off(hba)) {
+               err = phy_power_on(phy);
+               if (err) {
+                       dev_err(hba->dev, "%s: failed PHY power on: %d\n",
+                               __func__, err);
+                       return err;
+               }
 
-       err = ufs_qcom_enable_lane_clks(host);
-       if (err)
-               goto out;
+               err = ufs_qcom_enable_lane_clks(host);
+               if (err)
+                       return err;
 
-       hba->is_sys_suspended = false;
+       } else if (!ufs_qcom_is_link_active(hba)) {
+               err = ufs_qcom_enable_lane_clks(host);
+               if (err)
+                       return err;
+       }
 
-out:
-       return err;
+       hba->is_sys_suspended = false;
+       return 0;
 }
 
 #ifdef CONFIG_MSM_BUS_SCALING
@@ -1020,8 +1005,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
                return 0;
 
        if (on && (status == POST_CHANGE)) {
-               phy_power_on(host->generic_phy);
-
                /* enable the device ref clock for HS mode*/
                if (ufshcd_is_hs_mode(&hba->pwr_info))
                        ufs_qcom_dev_ref_clk_ctrl(host, true);
@@ -1033,9 +1016,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
                if (!ufs_qcom_is_link_active(hba)) {
                        /* disable device ref_clk */
                        ufs_qcom_dev_ref_clk_ctrl(host, false);
-
-                       /* powering off PHY during aggressive clk gating */
-                       phy_power_off(host->generic_phy);
                }
 
                vote = host->bus_vote.min_bw_vote;
@@ -1049,6 +1029,41 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
        return err;
 }
 
+static int
+ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+       struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
+
+       /* Currently this code only knows about a single reset. */
+       WARN_ON(id);
+       ufs_qcom_assert_reset(host->hba);
+       /* provide 1ms delay to let the reset pulse propagate. */
+       usleep_range(1000, 1100);
+       return 0;
+}
+
+static int
+ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+       struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
+
+       /* Currently this code only knows about a single reset. */
+       WARN_ON(id);
+       ufs_qcom_deassert_reset(host->hba);
+
+       /*
+        * after reset deassertion, phy will need all ref clocks,
+        * voltage, current to settle down before starting serdes.
+        */
+       usleep_range(1000, 1100);
+       return 0;
+}
+
+static const struct reset_control_ops ufs_qcom_reset_ops = {
+       .assert = ufs_qcom_reset_assert,
+       .deassert = ufs_qcom_reset_deassert,
+};
+
 #define        ANDROID_BOOT_DEV_MAX    30
 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
 
@@ -1093,6 +1108,17 @@ static int ufs_qcom_init(struct ufs_hba *hba)
        host->hba = hba;
        ufshcd_set_variant(hba, host);
 
+       /* Fire up the reset controller. Failure here is non-fatal. */
+       host->rcdev.of_node = dev->of_node;
+       host->rcdev.ops = &ufs_qcom_reset_ops;
+       host->rcdev.owner = dev->driver->owner;
+       host->rcdev.nr_resets = 1;
+       err = devm_reset_controller_register(dev, &host->rcdev);
+       if (err) {
+               dev_warn(dev, "Failed to register reset controller\n");
+               err = 0;
+       }
+
        /*
         * voting/devoting device ref_clk source is time consuming hence
         * skip devoting it during aggressive clock gating. This clock