#define IPR_SUBS_DEV_ID_2780 0x0264
#define IPR_SUBS_DEV_ID_5702 0x0266
#define IPR_SUBS_DEV_ID_5703 0x0278
-#define IPR_SUBS_DEV_ID_572E 0x028D
-#define IPR_SUBS_DEV_ID_573E 0x02D3
-#define IPR_SUBS_DEV_ID_573D 0x02D4
+#define IPR_SUBS_DEV_ID_572E 0x028D
+#define IPR_SUBS_DEV_ID_573E 0x02D3
+#define IPR_SUBS_DEV_ID_573D 0x02D4
#define IPR_SUBS_DEV_ID_571A 0x02C0
#define IPR_SUBS_DEV_ID_571B 0x02BE
-#define IPR_SUBS_DEV_ID_571E 0x02BF
+#define IPR_SUBS_DEV_ID_571E 0x02BF
#define IPR_SUBS_DEV_ID_571F 0x02D5
#define IPR_SUBS_DEV_ID_572A 0x02C1
#define IPR_SUBS_DEV_ID_572B 0x02C2
#define IPR_SUBS_DEV_ID_57B4 0x033B
#define IPR_SUBS_DEV_ID_57B2 0x035F
#define IPR_SUBS_DEV_ID_57C6 0x0357
+#define IPR_SUBS_DEV_ID_57CC 0x035C
#define IPR_SUBS_DEV_ID_57B5 0x033C
#define IPR_SUBS_DEV_ID_57CE 0x035E
#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
+#define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
unsigned long dump_addr_reg;
unsigned long dump_data_reg;
-#define IPR_ENDIAN_SWAP_KEY 0x000C0C00
+#define IPR_ENDIAN_SWAP_KEY 0x00080800
unsigned long endian_swap_reg;
};
u16 sis_type;
#define IPR_SIS32 0x00
#define IPR_SIS64 0x01
+ u16 bist_method;
+#define IPR_PCI_CFG 0x00
+#define IPR_MMIO 0x01
const struct ipr_chip_cfg_t *cfg;
};