Kalle Valo says:

[sfrench/cifs-2.6.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu_regs.h

diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
index 438b65ba96405ccd48decf12fb78fbff8db95539..35bde14047937ab52416899edfc8a20f83c2073b 100644 (file)
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
@@ -135,6 +135,7 @@
 #define REG_CAL_TIMER                  0x003c
 #define REG_ACLK_MON                   0x003e
 #define REG_GPIO_MUXCFG                        0x0040
+#define  GPIO_MUXCFG_IO_SEL_ENBT       BIT(5)
 #define REG_GPIO_IO_SEL                        0x0042
 #define REG_MAC_PINMUX_CFG             0x0043
 #define REG_GPIO_PIN_CTRL              0x0044
@@ -391,6 +392,7 @@
 #define REG_CPWM                       0x012f
 #define REG_FWIMR                      0x0130
 #define REG_FWISR                      0x0134
+#define REG_FTIMR                      0x0138
 #define REG_PKTBUF_DBG_CTRL            0x0140
 #define REG_PKTBUF_DBG_DATA_L          0x0144
 #define REG_PKTBUF_DBG_DATA_H          0x0148
@@ -440,6 +442,9 @@
 
 #define REG_FIFOPAGE                   0x0204
 #define REG_TDECTRL                    0x0208
+
+#define REG_DWBCN0_CTRL_8188F          REG_TDECTRL
+
 #define REG_TXDMA_OFFSET_CHK           0x020c
 #define  TXDMA_OFFSET_DROP_DATA_EN     BIT(9)
 #define REG_TXDMA_STATUS               0x0210
@@ -925,6 +930,7 @@
 
 #define REG_FPGA0_XA_LSSI_READBACK     0x08a0  /* Tranceiver LSSI Readback */
 #define REG_FPGA0_XB_LSSI_READBACK     0x08a4
+#define REG_FPGA0_PSD_REPORT           0x08b4
 #define REG_HSPI_XA_READBACK           0x08b8  /* Transceiver A HSPI read */
 #define REG_HSPI_XB_READBACK           0x08bc  /* Transceiver B HSPI read */
 
@@ -936,6 +942,7 @@
 #define REG_RFE_PATH_SELECT            0x0940  /* 8723BU */
 #define REG_RFE_BUFFER                 0x0944  /* 8723BU */
 #define REG_S0S1_PATH_SWITCH           0x0948  /* 8723BU */
+#define REG_OFDM_RX_DFIR               0x954
 
 #define REG_CCK0_SYSTEM                        0x0a00
 #define  CCK0_SIDEBAND                 BIT(4)
@@ -946,6 +953,13 @@
 #define  CCK0_AFE_RX_ANT_A             0
 #define  CCK0_AFE_RX_ANT_B             (BIT(24) | BIT(26))
 
+#define REG_CCK_PD_THRESH                      0x0a0a
+#define  CCK_PD_TYPE1_LV0_TH           0x40
+#define  CCK_PD_TYPE1_LV1_TH           0x83
+#define  CCK_PD_TYPE1_LV2_TH           0xcd
+#define  CCK_PD_TYPE1_LV3_TH           0xdd
+#define  CCK_PD_TYPE1_LV4_TH           0xed
+
 #define REG_CONFIG_ANT_A               0x0b68
 #define REG_CONFIG_ANT_B               0x0b6c
 
@@ -965,6 +979,7 @@
 
 #define REG_OFDM0_FA_RSTC              0x0c0c
 
+#define REG_OFDM0_XA_RX_AFE            0x0c10
 #define REG_OFDM0_XA_RX_IQ_IMBALANCE   0x0c14
 #define REG_OFDM0_XB_RX_IQ_IMBALANCE   0x0c1c
 
@@ -1011,6 +1026,9 @@
 #define  OFDM_LSTF_MASK                        0x70000000
 
 #define REG_OFDM1_TRX_PATH_ENABLE      0x0d04
+#define REG_OFDM1_CFO_TRACKING         0x0d2c
+#define REG_OFDM1_CSI_FIX_MASK1                0x0d40
+#define REG_OFDM1_CSI_FIX_MASK2                0x0d44
 
 #define REG_TX_AGC_A_RATE18_06         0x0e00
 #define REG_TX_AGC_A_RATE54_24         0x0e04
@@ -1202,6 +1220,7 @@
 #define RF6052_REG_UNKNOWN_43          0x43
 #define RF6052_REG_UNKNOWN_55          0x55
 #define RF6052_REG_UNKNOWN_56          0x56
+#define RF6052_REG_RXG_MIX_SWBW                0x87
 #define RF6052_REG_S0S1                        0xb0
 #define RF6052_REG_UNKNOWN_DF          0xdf
 #define RF6052_REG_UNKNOWN_ED          0xed