Merge branch 'rc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuil...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / rs400.c

diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 1a41cb268b72c7ac6594f74ee80ccc47325b4ce7..f454c9a5e7f22269a9ffe0618d87f1a74e05f276 100644 (file)
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -57,7 +57,9 @@ void rs400_gart_adjust_size(struct radeon_device *rdev)
        }
        if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
                /* FIXME: RS400 & RS480 seems to have issue with GART size
-                * if 4G of system memory (needs more testing) */
+                * if 4G of system memory (needs more testing)
+                */
+               /* XXX is this still an issue with proper alignment? */
                rdev->mc.gtt_size = 32 * 1024 * 1024;
                DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
        }
@@ -243,8 +245,6 @@ int rs400_mc_wait_for_idle(struct radeon_device *rdev)
 
 void rs400_gpu_init(struct radeon_device *rdev)
 {
-       /* FIXME: HDP same place on rs400 ? */
-       r100_hdp_reset(rdev);
        /* FIXME: is this correct ? */
        r420_pipes_init(rdev);
        if (rs400_mc_wait_for_idle(rdev)) {
@@ -265,6 +265,7 @@ void rs400_mc_init(struct radeon_device *rdev)
        r100_vram_init_sizes(rdev);
        base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
        radeon_vram_location(rdev, &rdev->mc, base);
+       rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
        radeon_gtt_location(rdev, &rdev->mc);
        radeon_update_bandwidth_info(rdev);
 }
@@ -433,7 +434,7 @@ int rs400_resume(struct radeon_device *rdev)
        /* setup MC before calling post tables */
        rs400_mc_program(rdev);
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
                        RREG32(R_0007C0_CP_STAT));
@@ -458,7 +459,6 @@ int rs400_suspend(struct radeon_device *rdev)
 
 void rs400_fini(struct radeon_device *rdev)
 {
-       radeon_pm_fini(rdev);
        r100_cp_fini(rdev);
        r100_wb_fini(rdev);
        r100_ib_fini(rdev);
@@ -497,7 +497,7 @@ int rs400_init(struct radeon_device *rdev)
                        return r;
        }
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev,
                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
@@ -509,8 +509,6 @@ int rs400_init(struct radeon_device *rdev)
 
        /* Initialize clocks */
        radeon_get_clock_info(rdev->ddev);
-       /* Initialize power management */
-       radeon_pm_init(rdev);
        /* initialize memory controller */
        rs400_mc_init(rdev);
        /* Fence driver */