drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2dcae9f24a85eda1fd01d4ea1bc9235beb3b1c1d..1878c4967529b1309e2e99dd8c81ecf1ea771647 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2373,6 +2373,7 @@ enum i915_power_well_id {
 
 #define GAMT_CHKN_BIT_REG      _MMIO(0x4ab8)
 #define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING     (1<<28)
+#define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT       (1<<24)
 
 #if 0
 #define PRB0_TAIL      _MMIO(0x2030)
@@ -2491,6 +2492,7 @@ enum i915_power_well_id {
 # define _3D_CHICKEN2_WM_READ_PIPELINED                        (1 << 14)
 #define _3D_CHICKEN3   _MMIO(0x2090)
 #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL            (1 << 10)
+#define  _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE       (1 << 5)
 #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL         (1 << 5)
 #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)      ((x)<<1) /* gen8+ */
 #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH  (1 << 1) /* gen6 */
@@ -2938,6 +2940,9 @@ enum i915_power_well_id {
 #define ILK_DPFC_CHICKEN       _MMIO(0x43224)
 #define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)
 #define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION    (1<<23)
+#define   GLK_SKIP_SEG_EN              (1<<12)
+#define   GLK_SKIP_SEG_COUNT_MASK      (3<<10)
+#define   GLK_SKIP_SEG_COUNT(x)                ((x)<<10)
 #define ILK_FBC_RT_BASE                _MMIO(0x2128)
 #define   ILK_FBC_RT_VALID     (1<<0)
 #define   SNB_FBC_FRONT_BUFFER (1<<1)
@@ -6922,6 +6927,10 @@ enum {
 #define  GLK_CL1_PWR_DOWN      (1 << 11)
 #define  GLK_CL0_PWR_DOWN      (1 << 10)
 
+#define CHICKEN_MISC_4         _MMIO(0x4208c)
+#define   FBC_STRIDE_OVERRIDE  (1 << 13)
+#define   FBC_STRIDE_MASK      0x1FFF
+
 #define _CHICKEN_PIPESL_1_A    0x420b0
 #define _CHICKEN_PIPESL_1_B    0x420b4
 #define  HSW_FBCQ_DIS                  (1 << 22)
@@ -7023,6 +7032,7 @@ enum {
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0                           _MMIO(0x7300)
+#define CNL_HDC_CHICKEN0                       _MMIO(0xE5F0)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE        (1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE            (1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED       (1<<11)
@@ -7476,6 +7486,7 @@ enum {
 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
 #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
+#define  CNP_PWM_CGE_GATING_DISABLE (1<<13)
 #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
 
 /* CPU: FDI_TX */
@@ -8054,6 +8065,7 @@ enum {
 #define GEN7_ROW_CHICKEN2              _MMIO(0xe4f4)
 #define GEN7_ROW_CHICKEN2_GT2          _MMIO(0xf4f4)
 #define   DOP_CLOCK_GATING_DISABLE     (1<<0)
+#define   PUSH_CONSTANT_DEREF_DISABLE  (1<<8)
 
 #define HSW_ROW_CHICKEN3               _MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
@@ -8065,6 +8077,7 @@ enum {
 #define   HSW_SAMPLE_C_PERFORMANCE     (1<<9)
 #define   GEN8_CENTROID_PIXEL_OPT_DIS  (1<<8)
 #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC  (1<<5)
+#define   CNL_FAST_ANISO_L1_BANKING_FIX        (1<<4)
 #define   GEN8_SAMPLER_POWER_BYPASS_DIS        (1<<1)
 
 #define GEN9_HALF_SLICE_CHICKEN7       _MMIO(0xe194)